summaryrefslogtreecommitdiffstats
path: root/src/intel
Commit message (Collapse)AuthorAgeFilesLines
* intel/perf: report query split for mdapiLionel Landwerlin2020-01-163-2/+18
| | | | | | | | | | | | | | | Also forgotten in the initial implementation. v2: Report begin timestamp scaled by the timestamp frequency (Windows behavior) v3: Rename split to disjoint to match GL terminology (Tapani) Signed-off-by: Lionel Landwerlin <[email protected]> Cc: <[email protected]> Acked-by: Tapani Pälli <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3112> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3112>
* intel/perf: expose timestamp begin for mdapiLionel Landwerlin2020-01-163-0/+9
| | | | | | | | | | | This was forgotten in the initial implementation. v2: ensure the value is written for both GL & Vulkan queries Signed-off-by: Lionel Landwerlin <[email protected]> Cc: <[email protected]> Acked-by: Tapani Pälli <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3112>
* anv: set depth stall enabled when depth flush enabled on gen12Tapani Pälli2020-01-162-0/+19
| | | | | | | | | | This implements HW workaround #1409600907 for anv driver. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3378> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3378>
* anv: implement another workaround for non pipelined statesLionel Landwerlin2020-01-161-0/+12
| | | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3408> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3408>
* genxml: add new Gen11+ PIPE_CONTROL fieldLionel Landwerlin2020-01-162-0/+2
| | | | | | | | | PIPE_CONTROL gained a new field in its first DWORD on Gen11. We had no use for it so far, but we start using it on Gen12. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3408>
* intel/compiler: Fix illegal mutation in get_nir_image_intrinsic_imageKenneth Graunke2020-01-151-3/+6
| | | | | | | | | | | | | | | | | | | | | | | get_nir_image_intrinsic_image() was incorrectly mutating the value held by the register which holds the intrinsic's first source (image index). If this happened to be the register for an SSA def which is also used elsewhere in the program, this meant that we would clobber that value in subsequent uses. Note that this only affects i965, because neither anv nor iris use the binding table start sections, so nothing is ever added here. Fixes KHR-GL46.compute_shader.resources-max on i965 with Eric Anholt's MR !3240 applied. That MR reorders SSBOs and ABOs, so that test uses image 0 and SSBO 0, causing this code to brilliantly add binding table index 45 to both the image (correct) and the SSBO (bzzt, wrong!). Fixes: 09f1de97a76 ("anv,i965: Lower away image derefs in the driver") Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3404> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3404>
* anv: Enable Vulkan 1.2 supportIván Briano2020-01-157-19/+20
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* anv: Implement the new core version property queriesJason Ekstrand2020-01-151-152/+261
| | | | | | | | | Vulkan 1.2 introduces some new structures to get the properties and features of a device from extensions that were promoted to core in 1.1 and 1.2. This commit implements the new property queries and makes all of the corresponding extension queries map to them. Reviewed-by: Iván Briano <[email protected]>
* anv: Implement the new core version feature queriesJason Ekstrand2020-01-151-56/+156
| | | | | | | | | Vulkan 1.2 introduces some new structures to get the properties and features of a device from extensions that were promoted to core in 1.1 and 1.2. This commit implements the new feature queries and makes all of the corresponding extension queries map to them. Reviewed-by: Iván Briano <[email protected]>
* anv,nir: Lower quad_broadcast with dynamic index in NIRJason Ekstrand2020-01-151-0/+1
| | | | | | | This is required for the subgroupBroadcastDynamicId feature that was added in Vulkan 1.2. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* anv: Bump the patch version to 131Jason Ekstrand2020-01-151-1/+1
|
* anv: fix pipeline switch back for non pipelined statesLionel Landwerlin2020-01-151-13/+8
| | | | | | | | | | | | | | Setting state base address can happen even before pipeline is selected. Also we must ensure it is set to 3D for Gen12, we can't switch back to an invalid pipeline value (UINT32_MAX). v2: Reuse helpers (Jason) Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: b34422db5e66 ("anv: Implement Gen12 workaround for non pipelined state") Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3396> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3396>
* i965: Reuse the new core glsl_count_dword_slots().Eric Anholt2020-01-142-54/+2
| | | | | | | | | The only difference I could see was treating interfaces like structs. Maintain that case. Reviewed-by: Kristian H. Kristensen <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3297> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3297>
* vulkan/wsi: Add a driconf option to force WSI to advertise BGRA8_UNORM firstJason Ekstrand2020-01-141-0/+1
| | | | | | | | | | | The Aztec Ruins benchmark just grabs the first format in the list and SRGB causes it to render washed out. With this workaround, it renders the same as OpenGL. Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3350> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3350>
* intel/fs: Only use SLM fence in compute shadersCaio Marcelo de Oliveira Filho2020-01-141-0/+3
| | | | | | | Fixes: b390ff35170 ("intel/fs: Add support for SLM fence in Gen11") Fixes: e142061399c ("intel/fs: Implement scoped_memory_barrier") Reviewed-by: Jason Ekstrand <[email protected]>
* anv: only use VkSamplerCreateInfo::compareOp if enabledLionel Landwerlin2020-01-141-1/+3
| | | | | | | | | | | | | | | The spec says nothing about the validity of the compareOp field when compareEnable is false. v2: use vulkan enum to pick default value (Caio) Signed-off-by: Lionel Landwerlin <[email protected]> Cc: <[email protected]> Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2350 Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3387> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3387>
* nir/lower_gs_intrinsics: add option for per-stream countsRhys Perry2020-01-141-1/+1
| | | | | | | Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2422> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2422>
* anv: Implement Gen12 workaround for non pipelined stateLionel Landwerlin2020-01-141-0/+27
| | | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3365> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3365>
* intel: Use similar brand strings to the Windows driversKenneth Graunke2020-01-132-17/+17
| | | | | | | | | | | | | | | This updates our product name strings to match the ones reported by the Windows driver, which is typically the marketing name. We retain a platform abbreviation and GT level in parenthesis so that we're able to distinguish similar parts more easily, helping us better understand at a glance which GPU a bug reporter has. Acked-by: Matt Turner <[email protected]> Acked-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3371> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3371>
* anv: Memset array propertiesJason Ekstrand2020-01-131-0/+5
| | | | | | | | | | | This is probably better than possibly leaving those bytes uninitialized even if the app will theoretically not use them. Cc: [email protected] Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Ivan Briano <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3369> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3369>
* anv: Don't over-advertise descriptor indexing featuresJason Ekstrand2020-01-131-15/+17
| | | | | | | | | We should only advertise sub-features if we advertise the extension. Fixes: 6e230d7607f "anv: Implement VK_EXT_descriptor_indexing" Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Ivan Briano <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3369>
* intel/blorp: Fill out all the dwords of MI_ATOMICJason Ekstrand2020-01-131-0/+4
| | | | | | | | | This makes us valgrind clean again. Fixes: 9175c7058efb "intel/blorp: Make blorp update the clear color..." Reviewed-by: Lionel Landwerlin <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3366> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3366>
* anv: set stencil layout for input attachmentsLionel Landwerlin2020-01-131-6/+14
| | | | | | | | | | | | | | If an input attachment has a stencil format, we need to set this. v2: Fish out VkAttachmentReferenceStencilLayoutKHR from VkAttachmentReference2KHR::pNext (Jason) Signed-off-by: Lionel Landwerlin <[email protected]> Reported-by: Samuel Pitoiset <[email protected]> Fixes: c1c346f16673 ("anv: implement VK_KHR_separate_depth_stencil_layouts") Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2891> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2891>
* anv: Drop an unused variableJason Ekstrand2020-01-131-1/+0
|
* nir/lower_atomics_to_ssbo: Also lower barriersJason Ekstrand2020-01-131-1/+0
| | | | | | | | | | | This is more correct for a pass which is supposed to completely lower away atomic counters. It also lets us stop supporting atomic counter barriers in most of the drivers. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307>
* nir: Rename nir_intrinsic_barrier to control_barrierJason Ekstrand2020-01-132-3/+3
| | | | | | | | This is a more explicit name now that we don't want it to be doing any memory barrier stuff for us. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307>
* intel/nir: Stop adding redundant barriersJason Ekstrand2020-01-131-14/+0
| | | | | | | | | | Now that both GLSL and SPIR-V are adding shared and tcs_patch barriers (as appropreate) prior to the nir_intrinsic_barrier, we don't need to do it ourselves in the back-end. This reverts commit 26e950a5de01564e3b5f2148ae994454ae5205fe. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307>
* nir: Add a new memory_barrier_tcs_patch intrinsicJason Ekstrand2020-01-132-0/+6
| | | | | | | | | | | Right now, it's implemented as a no-op for everyone. For most drivers, it's a switch case in the NIR -> whatever which just breaks. For ir3, they already have code to delete tessellation barriers so we just add a case to also delete memory_barrier_tcs_patch. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307>
* intel/vec4: Support scoped_memory_barrierJason Ekstrand2020-01-131-1/+2
| | | | | | Fixes: 06aecb14c0476 "anv: Implement VK_KHR_vulkan_memory_model" Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307>
* intel/fs: Make implied_mrf_writes() an fs_inst method.Francisco Jerez2020-01-107-18/+17
| | | | | | | | | | | | | | | This will be convenient in a later commit enabling SIMD32 fragment shaders, and happens to fix the calculation for MATH instructions which is currently inaccurate for SIMD-lowered instructions on Gen4-5 platforms (all of them on Gen4 in SIMD16 mode), since it was based on the shader's dispatch width rather than on the actual execution size of the instruction. This causes some shader-db noise on Gen4 due to the more compact register allocation interacting with the SEND dependency workarounds, but otherwise no major changes. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/fs/cse: Fix non-deterministic behavior due to inaccurate liveness ↵Francisco Jerez2020-01-102-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | calculation. The liveness calculation done by the local CSE pass in order to prune AEB entries whose sources are no longer live is currently inaccurate, because the live intervals are calculated once at the beginning of the pass, so they don't take into account any of the copy instructions inserted by the CSE pass as it makes progress. However the IP counter used in that calculation is based on the start_ip of the basic block, which is updated automatically whenever any instructions are inserted into the CFG. This causes the IP counter and liveness intervals to get out of sync in programs with multiple basic blocks, causing the CSE pass to toss AEB entries prematurely, which can lead to missed optimization opportunities rather non-deterministically. On BDW this leads to the following shader-db changes: total instructions in shared programs: 14952488 -> 14951763 (-0.00%) instructions in affected programs: 45416 -> 44691 (-1.60%) helped: 40 HURT: 4 total spills in shared programs: 20989 -> 20970 (-0.09%) spills in affected programs: 103 -> 84 (-18.45%) helped: 3 HURT: 0 total fills in shared programs: 24981 -> 24926 (-0.22%) fills in affected programs: 127 -> 72 (-43.31%) helped: 3 HURT: 0 In addition it avoids a number of regressions in combination with some of the optimization changes I'm working on for SIMD32, which would have made CSE more effective... Causing it to be less effective elsewhere in the program astonishingly. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/fs: Fix nir_intrinsic_load_barycentric_at_sample for SIMD32.Francisco Jerez2020-01-101-1/+1
| | | | | | | | | | | | | For uniform sample ID, only the first channel of msg_data will be initialized. We need to pass that component only to the SEND message for SIMD lowering to unzip the descriptor source correctly. Fixes several dozens of conformance test failures with SIMD32 fragment shaders enabled, including: dEQP-GLES31.functional.shaders.multisample_interpolation.interpolate_at_sample.dynamic_sample_number.* Reviewed-by: Kenneth Graunke <[email protected]>
* intel/fs/gen8+: Fix r127 dst/src overlap RA workaround for EOT message payload.Francisco Jerez2020-01-101-5/+11
| | | | | | | | | | | | | | | | | | | | | | | The problem occured when the return payload of a SIMD8 SEND instruction was re-used as source payload of an EOT SEND message. In such cases the interference edge added by that workaround between the payload and grf127_send_hack_node would have no effect, because the payload would be allocated to a fixed range of registers containing r127 by the special handling of EOT message payloads in the same function. This would cause things to blow up if the source payload of the first SIMD8 message ended up being allocated to a range which happened to overlap the destination. Fix it by avoiding r127 altogether in the allocation of EOT message payloads. The problem can be reproduced on ICL with the fp-indirections2 Piglit test-case in combination with the other optimizer changes of this series. Fixes: 232ed8980217 "i965/fs: Register allocator shoudn't use grf127 for sends dest" Cc: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/fs/gen11+: Handle ROR/ROL in lower_simd_width().Francisco Jerez2020-01-101-0/+2
| | | | | | | | | | | | | | | | | | Prevents invalid code from being emitted for ROR/ROL instructions in SIMD32 shaders. The problem can be reproduced with the following tests while forcing SIMD32 to be used for fragment shaders: piglit.shaders.glsl-rotate-left piglit.shaders.glsl-rotate-right However the issue could occur in production already with compute shaders and a workgroup size large enough to trigger SIMD32 dispatch. Fixes: 83fdec0f0de "intel/compiler: Enable the emission of ROR/ROL instructions" Cc: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* anv: Re-use flush_descriptor_sets in flush_compute_stateJason Ekstrand2020-01-091-65/+25
| | | | | | | | | | There's no reason to hand-roll all of the memory re-allocation fall-back code for compute shaders. It's just duplicated complexity. This also makes it more clear in flush_compute_state where the MEDIA_INTERFACE_DESCRIPTOR_LOAD command gets emitted relative to other packets in the command stream. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* anv: Flag descriptors dirty when gl_NumWorkgroups is usedJason Ekstrand2020-01-091-1/+8
| | | | | Cc: [email protected] Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* anv: Don't add dynamic state base address to push constants on Gen7Jason Ekstrand2020-01-091-14/+20
| | | | | | | | | | | | Because Gen7 push constants are already relative to dynamic state base address, they aren't really an address. It's deceptive to return an address from the helper function. Instead, let's leave it as a special-case in the gen7-11 helper; we don't need the helper for code de-duplication for Gen7 anyway. Fixes: 67d2cb3e9367a "anv: Add get_push_range_address() helper" Closes: #2323 Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* genxml: Remove a non-existant HW bitJason Ekstrand2020-01-093-3/+0
|
* anv: fix intel perf queries availability writesLionel Landwerlin2020-01-091-14/+5
| | | | | | | | | The availability is not written at the location changed in ee6fbb95a74d... Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: ee6fbb95a74d ("anv: Properly handle host query reset of performance queries") Reviewed-by: Jason Ekstrand <[email protected]>
* anv: don't close invalid syncfd semaphoreLionel Landwerlin2020-01-081-1/+2
| | | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Cc: <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/disasm: Fix decoding of src0 of SENDSJason Ekstrand2020-01-081-1/+1
| | | | | | | | | There is no instruction field for the register file for src0 because it's always GRF. Reviewed-by: Kenneth Graunke <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3309> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3309>
* intel/nir: Add a memory barrier before barrier()Jason Ekstrand2020-01-071-0/+14
| | | | | | | | | | | Our barrier instruction does not implicitly do a memory fence but the GLSL barrier() intrinsic is supposed to. The easiest back-portable solution is to just add the NIR barriers. We'll sort this out more properly in later commits. Cc: [email protected] Closes: #2138 Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* anv: Only enable EWA LOD algorithm when doing anisotropic filtering.Kenneth Graunke2020-01-041-1/+2
| | | | | | | | | Updated documentation renames "Anisotropic Algorithm" to "LOD Algorithm" and adds a note for Gen9+ saying "The EWA Algorithm should only be enabled for Anisotropic Filtering modes." and indicating that the extra accuracy shouldn't be necessary for other modes, and comes at a cost. Reviewed-by: Jason Ekstrand <[email protected]>
* anv: Allow HiZ in TRANSFER_SRC_OPTIMAL on Gen8-9Jason Ekstrand2020-01-042-11/+18
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/blorp: Use the source format when using blorp_copy with HiZJason Ekstrand2020-01-041-1/+9
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* blorp: Allow reading with HiZJason Ekstrand2020-01-041-2/+6
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* blorp: Stop whacking Z24 depth to BGRA8Jason Ekstrand2020-01-041-11/+0
| | | | | | | | | The shader code required to do this is int(sat(x) * UINT24_MAX) which isn't really worth all the effort to avoid. Doing the format conversion, on the other hand, prevents us from sampling with HiZ which is something that we very much want on gen8-9 where we can. Reviewed-by: Kenneth Graunke <[email protected]>
* anv: Ignore some CreateInfo structs when rasterization is disabledCaio Marcelo de Oliveira Filho2020-01-032-18/+38
| | | | | | | | | | | | | | | | | | | | According to the description of VkGraphicsPipelineCreateInfo(), pViewportState, pMultisampleState, pDepthStencilState and pColorBlendState must be ignored when rasterization is not enabled. This avoids potentially invalid pointers being dereferenced when rasterization is disabled. Tested with `demos_x64 VK_Parameter_Zoo` from Renderdoc repository. v2: Don't store the `raster_enabled` as part of anv_pipeline, just query it from the create info. This avoids storing a state that's only used during pipeline creation. (Jason) Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2258 Cc: <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> [v1] Reviewed-by: Lionel Landwerlin <[email protected]> [v1] Reviewed-by: Jason Ekstrand <[email protected]>
* anv: Drop unused function parameterCaio Marcelo de Oliveira Filho2020-01-031-3/+2
| | | | | | Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: Drop unneeded struct keywordsJason Ekstrand2020-01-0310-18/+18
| | | | | | | | | All VkFoo structs are typedef'd to not need the struct keyword. Leaving it in there is just extra characters and breaks Vulkan's aliasing when stuff gets promoted to core versions. It's better to just never use struct for VkFoo. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-13 11:57:09 +0000