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* intel/compiler: Cast to target type before shifting leftMichel Dänzer2019-10-241-1/+1
* intel/compiler: Don't left-shift by >= the number of bits of the typeMichel Dänzer2019-10-241-2/+2
* anv: fix error messageEric Engestrom2019-10-241-5/+2
* anv: implement VK_INTEL_performance_queryLionel Landwerlin2019-10-239-18/+535
* intel/perf: add mdapi writes for register perf countersLionel Landwerlin2019-10-231-0/+36
* intel/genxml: add RPSTAT register for core frequencyLionel Landwerlin2019-10-238-0/+40
* intel/genxml: add generic perf counters registersLionel Landwerlin2019-10-234-0/+72
* intel/perf: add support for querying kernel loaded configurationsLionel Landwerlin2019-10-232-27/+181
* intel/perf: move registers to their own headerLionel Landwerlin2019-10-233-25/+55
* intel/perf: extract register configurationLionel Landwerlin2019-10-233-16/+24
* intel/perf: expose some utility functionsLionel Landwerlin2019-10-232-31/+55
* intel/perf: add mdapi maker helperLionel Landwerlin2019-10-231-0/+28
* anv: fix unwind of vkCreateDevice failLionel Landwerlin2019-10-221-3/+3
* intel/compiler: Refactor disassembly of sources in 3src instructionSagar Ghuge2019-10-211-19/+10
* intel/compiler: Don't move immediate in registerSagar Ghuge2019-10-211-0/+38
* intel/compiler: Set bits according to source fileSagar Ghuge2019-10-211-2/+12
* intel/compiler: Add Immediate support for 3 source instructionSagar Ghuge2019-10-211-21/+32
* intel: Add missing entry for brw_nir_lower_alpha_to_coverage in MakefileSagar Ghuge2019-10-211-0/+1
* intel/compiler: Remove emit_alpha_to_coverage workaround from backendSagar Ghuge2019-10-212-84/+13
* nir: Add alpha_to_coverage lowering passSagar Ghuge2019-10-213-0/+171
* anv: fix memory leak on device destroyLionel Landwerlin2019-10-201-1/+11
* anv: fix vkUpdateDescriptorSets with inline uniform blocksLionel Landwerlin2019-10-191-3/+3
* intel/isl: Add isl_aux_usage_has_ccsJason Ekstrand2019-10-171-0/+7
* intel/isl: Add R10G10B10_FLOAT_A2_UNORM formatJordan Justen2019-10-174-0/+4
* intel/compiler: Report the number of non-spill/fill SEND messagesKenneth Graunke2019-10-171-5/+30
* intel/vec4: Don't try both sources as immediates for DPHIan Romanick2019-10-171-1/+1
* intel/isl: Add gen12 depth/stencil surface alignmentsJordan Justen2019-10-175-2/+123
* intel/isl: Select Y-tiling for stencil on gen12Jason Ekstrand2019-10-171-4/+7
* intel/genxml: Remove W-tiling on gen12Jason Ekstrand2019-10-172-1/+3
* intel/genxml,isl: Add gen12 stencil buffer changesJordan Justen2019-10-172-6/+52
* intel/genxml,isl: Add gen12 depth buffer changesJordan Justen2019-10-172-10/+14
* intel/genxml,isl: Add gen12 render surface state changesJordan Justen2019-10-172-12/+19
* intel/fs/gen12: Add tests for scoreboard passCaio Marcelo de Oliveira Filho2019-10-172-1/+864
* intel/common: include unistd.h for ioctl() prototype on SolarisAlan Coopersmith2019-10-161-0/+1
* anv: Advertise VK_KHR_spirv_1_4Caio Marcelo de Oliveira Filho2019-10-141-0/+1
* anv: add exported symbols checkEric Engestrom2019-10-131-0/+13
* intel/fs/gen12: Use TCS 8_PATCH mode.Kenneth Graunke2019-10-112-6/+8
* intel/fs/gen12: Implement gl_FrontFacing on gen12+.Jason Ekstrand2019-10-112-2/+25
* intel/fs/gen11+: Fix CS_OPCODE_CS_TERMINATE codegen.Francisco Jerez2019-10-112-8/+11
* intel/fs/gen12: Fix barrier codegen.Francisco Jerez2019-10-112-2/+7
* intel/eu: Don't set notify descriptor field of gateway barrier message.Francisco Jerez2019-10-111-1/+0
* intel/ir/gen12: Update assert in brw_stage_has_packed_dispatch().Francisco Jerez2019-10-111-1/+1
* intel/eu/validate/gen12: Don't blow up on indirect src0.Jason Ekstrand2019-10-111-1/+2
* intel/eu/validate/gen12: Validation fixes for SEND instruction.Francisco Jerez2019-10-111-22/+28
* intel/eu/validate/gen12: Fix validation of SYNC instruction.Francisco Jerez2019-10-111-1/+1
* intel/eu/validate/gen12: Implement integer multiply restrictions in EU valida...Francisco Jerez2019-10-111-0/+33
* intel/ir: Lower fpow on Gen12.Jordan Justen2019-10-111-0/+1
* intel/fs/gen12: Don't support source mods for 32x16 integer multiply.Francisco Jerez2019-10-111-0/+18
* intel/disasm: Disassemble register file of split SEND sources.Francisco Jerez2019-10-111-1/+4
* intel/disasm: Don't disassemble saturate control on SEND instructions.Francisco Jerez2019-10-111-2/+4
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