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* anv: Add and use color auxiliary buffer helpersNanley Chery2017-06-262-0/+32
| | | | | | | | | | | | | | v2: - Check for aux levels in layer helper (Jason Ekstrand) - Don't assert aux is present, return 0 if it isn't. - Use the helpers. v3: - Make the helpers aspect-agnostic (Jason Ekstrand) - Drop anv_image_has_color_aux() Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> (v2) Reviewed-by: Jason Ekstrand <[email protected]>
* intel/isl: Only create a CCS buffer if the image supports renderingNanley Chery2017-06-261-1/+1
| | | | | | | | v2: Omit the commit message. Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/isl: Limit CCS to one level and layer on gen7Nanley Chery2017-06-261-2/+7
| | | | | | | | | | v2 (Jason Ekstrand): - Remove Vulkan-specific terminology from the commit title. - Replace '== 7' with '<= 7' to hint that this is a new feature on BDW+. Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> (v1) Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp: Check for layer fast-clear restrictionNanley Chery2017-06-261-0/+5
| | | | | | | | v2: Update commit title (Jason Ekstrand) Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> (v1) Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp: Assert levels and layers are in rangeNanley Chery2017-06-262-4/+7
| | | | | | | | | | | | v2 (Jason Ekstrand): - Update commit title. - Check aux level and layer as well. v3 (Jason Ekstrand): - Move the non-aux layer check. Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> (v1) Reviewed-by: Jason Ekstrand <[email protected]>
* anv: use Mesa's u_atomic.h headerEric Engestrom2017-06-261-2/+3
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* anv/cnl: Don't write to Cache Mode Register 1 on gen10+Anuj Phogat2017-06-231-3/+1
| | | | | | | | | For PartialResolveDisableInVC field recommendation is to always set this to 0 and that's the default value of the bit. So, we have nothing left to write to CACHE_MODE_1. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: fix gen5 sampler border color state.Rafael Antognolli2017-06-221-20/+20
| | | | | | | | Based on the current code, gen5 and gen6 have the same sampler border color state struct. So fix the gen5 one to match gen6. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* aubinator: Dump sampler state pointers on gen6 too.Rafael Antognolli2017-06-221-0/+11
| | | | | | | | We already have a function to dump sampler states, so do that for gen6 too. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: Fix -Wswitch in anv_layout_to_aux_usage()Chad Versace2017-06-221-0/+3
| | | | | | | | anv_layout_to_aux_usage() lacked a case for VK_IMAGE_LAYOUT_SHARED_PRESENT_KHR. Add an unreachable case, because we don't support the extension. Acked-by: Jason Ekstrand <[email protected]>
* i965/CFL: Add PCI Ids for Coffee Lake.Anusha Srivatsa2017-06-222-0/+27
| | | | | | | | | | | | | | Coffee Lake has a gen9 graphics following KBL. From 3D perspective, CFL is a clone of KBL/SKL features. v2: Change commit message, correct alignment <Anuj Phogat> v3: Update IDs. v4: Initialize l3_banks, correct nomenclature <Anuj> Cc: Rodrigo Vivi <[email protected]> Signed-off-by: Anusha Srivatsa <[email protected]> Acked-by: Benjamin Widawsky <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* intel: Enable vulkan build for gen10Anuj Phogat2017-06-221-0/+4
| | | | | | | | This patch just enables building Vulkan libs for gen10. We still don't have gen 10 support enabled on Vulkan. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv/cnl: Generate and use gen10 functionsAnuj Phogat2017-06-224-1/+13
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv/cnl: Don't set FloatBlendOptimizationEnable{Mask}Anuj Phogat2017-06-221-3/+6
| | | | | | | This field is remove from CACHE_MODE_1 register in gen10. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv/cnl: Use GENX(xx) in place of GEN9_xxAnuj Phogat2017-06-221-8/+8
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv/cnl: Add #defines for MOCS and genX(x)Anuj Phogat2017-06-221-0/+14
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/genxml: Add Gen10 CACHE_MODE_1 definitionsAnuj Phogat2017-06-221-0/+18
| | | | | | | | | | Few of the fields in this register are changed as compared to gen9.xml. V2: Remove some fields which are not valid anymore. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: Rename StartInstanceLocation to StartingInstanceLocationAnuj Phogat2017-06-221-1/+1
| | | | | | | | This is required because we already have a macro defined with the name StartInstanceLocation. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: Rename IndirectStatePointer to BorderColorPointerAnuj Phogat2017-06-221-1/+1
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: Combine DataDWord{0, 1} fields in to ImmediateData fieldAnuj Phogat2017-06-221-2/+1
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: Add INSTDONE registers in gen10Anuj Phogat2017-06-221-0/+115
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: Add better support for MI_MATH in gen10Anuj Phogat2017-06-221-4/+65
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* anv: FORMAT_FEATURE_TRANSFER_SRC/DST_BIT_KHR not used with ↵Andres Gomez2017-06-221-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | VkFormatProperties.bufferFeatures VK_FORMAT_FEATURE_TRANSFER_[SRC|DST]_BIT_KHR is a flag value of the VkFormatFeatureFlagBits enum that can only be hold and checked against the linearTilingFeatures or optimalTilingFeatures members of the VkFormatProperties struct but not the bufferFeatures member. >From the Vulkan® 1.0.51, with the VK_KHR_maintenance1 extension, section 32.3.2 docs for VkFormatProperties: "* linearTilingFeatures is a bitmask of VkFormatFeatureFlagBits specifying features supported by images created with a tiling parameter of VK_IMAGE_TILING_LINEAR. * optimalTilingFeatures is a bitmask of VkFormatFeatureFlagBits specifying features supported by images created with a tiling parameter of VK_IMAGE_TILING_OPTIMAL. * bufferFeatures is a bitmask of VkFormatFeatureFlagBits specifying features supported by buffers." ... Bits which can be set in the VkFormatProperties features linearTilingFeatures, optimalTilingFeatures, and bufferFeatures are: typedef enum VkFormatFeatureFlagBits { ... VK_FORMAT_FEATURE_TRANSFER_SRC_BIT_KHR = 0x00004000, VK_FORMAT_FEATURE_TRANSFER_DST_BIT_KHR = 0x00008000, ... } VkFormatFeatureFlagBits; ... The following bits may be set in linearTilingFeatures and optimalTilingFeatures, specifying that the features are supported by images or image views created with the queried vkGetPhysicalDeviceFormatProperties::format: ... * VK_FORMAT_FEATURE_TRANSFER_SRC_BIT_KHR specifies that an image can be used as a source image for copy commands. * VK_FORMAT_FEATURE_TRANSFER_DST_BIT_KHR specifies that an image can be used as a destination image for copy commands and clear commands." Cc: Jason Ekstrand <[email protected]> Cc: Iago Toral Quiroga <[email protected]> Cc: Lionel Landwerlin <[email protected]> Signed-off-by: Andres Gomez <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/genxml: Use the same naming convention for Floating Point Mode.Rafael Antognolli2017-06-211-2/+2
| | | | | | | | In newer gens, this field has a prefix and the non-IEEEE-745 mode is called "Alternate", instead of simply "Alt". Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: Normalize URB Data field in WM_STATE.Rafael Antognolli2017-06-213-3/+3
| | | | | | | | | | On gen6+, this is called "Dispatch GRF Start Register For Constant/Setup Data 0", while on gen5 and lower it's called only "Dispatch GRF Start Register For URB Data", but it's essentially the same thing (URB data), so rename it to match newer gens and simplify the C code that handles it. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: Rename field on WM_STATE to match gen6+.Rafael Antognolli2017-06-213-3/+3
| | | | | | | | "Pixel Shader Kill Pixel" -> "Pixel Shader Kills Pixel", which is how it's called on newer gens. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: Normalize fields on WM_STATE.Rafael Antognolli2017-06-212-4/+4
| | | | | | | | | On gen4, WM_STATE only has one Kernel Start Pointer and one GRF Register Count, but we can make the code that handles this on multiple gens simpler if we add an index 0 to it too. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: Add missing field to CLIP_STATE.Rafael Antognolli2017-06-212-0/+5
| | | | | | | | | | | Just because it's not set doesn't mean that it doesn't exist. And since the field is there on newer gens, having it on gen5 simplifies the code when porting gen5 and lower. Also add missing value to API Mode on CLIP_STATE on gen4. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: Fix type of UserClipFlags ClipTest Enable Bitmask.Rafael Antognolli2017-06-213-3/+3
| | | | | | | | This is a bitmask, so it can't be a boolean. Also rename it so it matches gen6+. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: Add missing fields to CLIP_STATE on gen4-5.Rafael Antognolli2017-06-212-0/+2
| | | | | | | | These fields are set by brw_clip_unit, so we need them when converting to genxml. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: Normalize GS_STATE.Rafael Antognolli2017-06-211-1/+1
| | | | | | | Rename "Rendering Enable" to "Rendering Enabled", so it matches gen6+. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: compiler/i965: fix is_broxton checksLionel Landwerlin2017-06-205-6/+9
| | | | | | | | | | In 5f2fe9302c is_geminilake was introduced for the differenciate broxton from geminilake. Unfortunately I failed as verifying that is_broxton is throughout the code base to mean Gen9lp. Fixes: 5f2fe9302c ("intel: common: add flag to identify platforms by name") Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/cnl: Add l3 configuration for CannonlakeBen Widawsky2017-06-201-1/+20
| | | | | | | | | | | | | | | | | | V2 (Anuj): Squash the changes in one patch rebase on master. Address the review comments made by Francisco Jerez. Do the URB allocation per slice (not per bank). V3 (Anuj): Update the comment. Format the table as other l3 config tables. Signed-off-by: Ben Widawsky <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> --- V1 was sent out with the heading: "i965/cnl: Properly handle l3 configuration"
* i965: Add a variable for way size per bank in get_l3_way_size()Anuj Phogat2017-06-201-5/+4
| | | | | | | | | | Adding this variable better explains the computation of L3 way size in the function. V2: Use const variable for way_size_per_bank. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: Fix broxton 2x6 l3 configAnuj Phogat2017-06-201-0/+16
| | | | | | | | | | | The new table added in this patch matches with the table in gfxspecs. We were programming the wrong values earlier. V2: Update the comment. Cc: "17.1" <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* intel/blorp: Apply source offset in the TEX caseIan Romanick2017-06-201-0/+3
| | | | | | | | Previously the offset was only applied in the TXF case. Signed-off-by: Ian Romanick <[email protected]> Suggested-by: Jason Ekstrand <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp: Apply Gen4 coord. normalization after cubemap sizes are adjustedIan Romanick2017-06-201-9/+11
| | | | | | | | | Otherwise the values used for coordinate normalization use the wrong sizes. Signed-off-by: Ian Romanick <[email protected]> Suggested-by: Jason Ekstrand <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp: Set needs_(dst|src)_offset for Gen4 cubemapsJason Ekstrand2017-06-201-2/+6
| | | | | | | | | | | | | | | We call convert_to_single_slice so they may end up with a non-trivial offset that needs to be taken into account. v2 (idr): Also set needs_src_offset. Suggested by Jason. Fixes ES2-CTS.functional.texture.specification.basic_copyteximage2d.cube_rgba and ES2-CTS.functional.texture.specification.basic_copytexsubimage2d.cube_rgba on G45. Signed-off-by: Ian Romanick <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101284 Reviewed-by: Jason Ekstrand <[email protected]>
* intel: common: add number of thread per euLionel Landwerlin2017-06-192-2/+28
| | | | | | | This will be used by to normalize OA counters. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: common: express timestamps units in frequencyLionel Landwerlin2017-06-193-12/+14
| | | | | | | | | | | | | | Rather than storing the period as a double that looses some precision. Also fixes the Gen9LP timestamp frequency which is no 19200123 but 19200000 as pointed by Ville : https://lists.freedesktop.org/archives/intel-gfx/2017-April/125126.html Finally add the Cannonlake timestamp frequency. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: common: add flag to identify platforms by nameLionel Landwerlin2017-06-192-6/+24
| | | | | | | | The perf infrastructure needs to identify specific platforms, not just generations. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* anv: Fix L3 cache programming on Bay TrailJonas Kulla2017-06-191-1/+1
| | | | | | | | | | | Valid values for URBAllocation start at 32, so substract that before programming the register. This was missed when porting from the GL driver. Cc: "17.1" <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/isl/gen6: Allow arrayed stencilTopi Pohjolainen2017-06-171-1/+0
| | | | | | | | Nothing prevents arrayed stencil surfaces even though hardware doesn't support mipmapping. Reviewed-by: Nanley Chery <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* genxml: The viewport state offset is actually an address.Rafael Antognolli2017-06-161-1/+1
| | | | | | | This fixes code generation on gen45. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* genxml: Rename fields to match gen6+.Rafael Antognolli2017-06-163-3/+3
| | | | | | | "Anti-aliasing Enable" to "Anti-Aliasing Enable". Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* genxml: Rename SF_STATE field to match gen6+.Rafael Antognolli2017-06-163-9/+9
| | | | | | | | | Rename "Use Point Width State" to "Point Width Source". It accepts the same values and has the same meaning as gen6+, so lets keep them with the same name to simplify the code. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/isl: Add the maximum surface size limitAnuj Phogat2017-06-161-0/+22
| | | | | | | | V2: Use 2^31 bytes (2GB) surface size limit on pre-gen9 and 2^38 bytes for gen9+. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/isl: Use uint64_t to store total surface sizeAnuj Phogat2017-06-162-2/+3
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/blorp: Work around Sandy Bridge occlusion query issueJason Ekstrand2017-06-141-0/+10
| | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* intel/isl: Properly set SeparateStencilBufferEnable on gen5-6Jason Ekstrand2017-06-141-3/+10
| | | | | | | On gen5-6, SeparateStencilBufferEnable and HierarchicalDepthBufferEnable come hand in hand and we have to set either both or neither. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
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