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* intel/compiler: Relax mixed type restriction for saturating immediatesIan Romanick2018-07-062-4/+22
* i965/vec4: Properly handle sign(-abs(x))Ian Romanick2018-07-061-1/+17
* i965/fs: Properly handle sign(-abs(x))Ian Romanick2018-07-061-3/+12
* python: Use the print functionMathieu Bridon2018-07-061-3/+5
* i965/vec4: Make the vec4_visitor::nir_emit_instr default case unreachableIan Romanick2018-07-051-2/+1
* intel/compiler: More DCE after loweringIan Romanick2018-07-051-0/+2
* python: Specify the JSON separatorsMathieu Bridon2018-07-051-1/+1
* intel: tools: remove drm-uapi definesLionel Landwerlin2018-07-051-29/+1
* intel: intel_dump_gpu: use simulator id in capturesLionel Landwerlin2018-07-052-2/+2
* intel: devinfo: add simulator idLionel Landwerlin2018-07-052-4/+48
* intel: tools: dump-gpu: dump 48-bit addressesScott D Phillips2018-07-052-167/+151
* intel: tools: import intel_aubdumpLionel Landwerlin2018-07-054-0/+1440
* intel: tools: update intel_aub.hLionel Landwerlin2018-07-051-0/+26
* intel: batch-decoder: add missing return lineLionel Landwerlin2018-07-051-1/+1
* intel: batch-decoder: don't asks for constant BO until decodingLionel Landwerlin2018-07-051-6/+11
* intel/batch-decoder: handle non-contiguous binding table / surface stateScott D Phillips2018-07-051-4/+14
* intel/tools/aubinator: aubinate ppgtt aubsScott D Phillips2018-07-051-1/+72
* intel: aubinator: handle GGTT mappingsLionel Landwerlin2018-07-051-13/+244
* intel: aubinator: drop the 1Tb GTT mappingLionel Landwerlin2018-07-051-55/+75
* intel: aubinator: rework register writes handlingLionel Landwerlin2018-07-051-28/+54
* intel: aubinator: remove standard input processing optionLionel Landwerlin2018-07-051-90/+12
* intel: aubinator: remove unused variablesLionel Landwerlin2018-07-051-5/+0
* i965: Fix output register sizes when variable ranges are interleavedNeil Roberts2018-07-041-7/+18
* i965/vec4: Don't cmod propagate from CMP to ADD if the writemask isn't compat...Ian Romanick2018-07-022-5/+87
* intel/compiler: Silence unused parameter warnings brw_nir.cIan Romanick2018-07-025-7/+6
* anv: Add support for the on-disk shader cacheJason Ekstrand2018-07-023-11/+126
* anv/pipeline_cache: Add a _locked suffix to a functionJason Ekstrand2018-07-021-14/+15
* anv: Add device-level helpers for searching for and uploading kernelsJason Ekstrand2018-07-023-79/+98
* anv/pipeline: Stop optimizing for not having a cacheJason Ekstrand2018-07-021-34/+31
* anv: Use a default pipeline cache if none is specifiedJason Ekstrand2018-07-025-18/+25
* anv: Be more careful about hashing pipeline layoutsJason Ekstrand2018-07-021-3/+38
* anv,intel: Enable nir_opt_large_constants for VulkanJason Ekstrand2018-07-023-0/+14
* anv: Add state setup support for shader constantsJason Ekstrand2018-07-023-19/+101
* anv: Add support for shader constant data to the pipeline cacheJason Ekstrand2018-07-024-0/+50
* anv/cmd_buffer: make descriptors dirty when emitting base state addressIago Toral Quiroga2018-07-021-0/+5
* anv/cmd_buffer: clean dirty push constants flag after emitting push constantsIago Toral Quiroga2018-07-021-0/+2
* anv/cmd_buffer: never shrink the push constant buffer sizeIago Toral Quiroga2018-07-021-1/+16
* anv: finish the binding_table_pool on destroyDevice when use_softpinJose Maria Casanova Crespo2018-06-291-0/+3
* intel/fs: Build 32-wide FS shaders.Francisco Jerez2018-06-281-11/+43
* intel/anv,blorp,i965: Implement the SKL 16x MSAA SIMD32 workaroundJason Ekstrand2018-06-282-2/+32
* intel/fs: Add fields to wm_prog_data for SIMD32 dispatchJason Ekstrand2018-06-284-1/+12
* intel/fs: Fix nir_intrinsic_load_helper_invocation for SIMD32.Francisco Jerez2018-06-281-5/+9
* intel/fs: Fix fs_builder::sample_mask_reg() for 32-wide FS dispatch.Francisco Jerez2018-06-281-3/+3
* intel/fs: Fix Gen6+ interpolation setup for SIMD32Francisco Jerez2018-06-281-56/+60
* intel/fs: Get rid of MOV_DISPATCH_TO_FLAGSJason Ekstrand2018-06-285-35/+8
* intel/fs: Emit MOV_DISPATCH_TO_FLAGS once for the centroid workaroundJason Ekstrand2018-06-282-50/+16
* intel/fs: Generalize the unlit centroid workaroundFrancisco Jerez2018-06-281-14/+8
* intel/fs: Fix sample id setup for SIMD32.Francisco Jerez2018-06-281-9/+25
* intel/fs: Fix Gen7 compressed source region alignment restriction for SIMD32Francisco Jerez2018-06-281-1/+7
* intel/fs: Implement 32-wide FS payload setup on Gen6+Francisco Jerez2018-06-281-67/+57
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