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* util: use C99 declaration in the for-loop set_foreach() macroEric Engestrom2018-10-252-4/+0
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* util: use C99 declaration in the for-loop hash_table_foreach() macroEric Engestrom2018-10-254-8/+0
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* anv: move variable to proper scope and mark as MAYBE_UNUSEDEric Engestrom2018-10-241-2/+1
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: use snprintf() instead of memset()+strcpy()Eric Engestrom2018-10-241-4/+3
| | | | | | | | | snprintf() guarantees that it will not write more chars than allowed, and that the string will be null-terminated, without the need to fill the whole thing with zeroes to begin with. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: drop unused includesEric Engestrom2018-10-241-3/+0
| | | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: Allow presenting via a different GPUAlex Smith2018-10-241-2/+2
| | | | | | | | | | | | | | | anv_GetPhysicalDeviceSurfaceSupportKHR will already return success for this, but anv_GetPhysicalDevice{Xcb,Xlib}PresentationSupportKHR do not. Apps which check for presentation support via the latter (all Feral Vulkan games at least) will therefore fail. This allows me to render on an Intel GPU and present to a display connected to an AMD card (tested HD 530 + Vega 64). v2: Rebase on current master. Signed-off-by: Alex Smith <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: Change src1 reg type to unsigned doublewordSagar Ghuge2018-10-232-3/+3
| | | | | | | | | | | To have uniform behavior while disassembling send(c) instruction use register type of unsigned doubleword for src1 when message descriptor is immediate value. Bspec does not specifiy anything for src1 immediate default type. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Sagar Ghuge <[email protected]>
* intel/decoders: fix end of batch limitLionel Landwerlin2018-10-233-9/+10
| | | | | | | | | | | | | Pointer arithmetic... v2: s/4/sizeof(uint32_t)/ (Eric) v3: Give bytes to print_batch() in error_decode (Lionel) Make clear what values we're dealing with in error_decode (Lionel) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> (v2) Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Fix decoding for partial STATE_BASE_ADDRESS updates.Kenneth Graunke2018-10-222-6/+42
| | | | | | | | | | | STATE_BASE_ADDRESS only modifies various bases if the "modify" bit is set. Otherwise, we want to keep the existing base address. Iris uses this for updating Surface State Base Address while leaving the others as-is. v2: Also update aubinator_viewer_decoder (caught by Lionel) Reviewed-by: Lionel Landwerlin <[email protected]>
* anv,radv: Trivially expose two new VK_GOOGLE extensionsJason Ekstrand2018-10-221-0/+2
| | | | | | | | | | | | This patch exposes support for the following two extensions: * VK_GOOGLE_decorate_string * VK_GOOGLE_hlsl_functionality1 There's nothing for the driver to do; it's all handled in spirv_to_nir. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107971 Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* anv: Define trampolines as the weak functionsJason Ekstrand2018-10-192-49/+21
| | | | | | | | | | | | | | | | | | | | | Instead of having weak references to the anv functions and separate trampoline functions with their own dispatch table, just make the trampoline functions weak. This gets rid of a dispatch table and potentially lets the compiler delete the unused weak function. The end result is a reduction in the .text section of 5.7K and a reduction in the .data section of 1.4K. Before: text data bss dec hex filename 3190329 282232 8960 3481521 351fb1 _install/lib64/libvulkan_intel.so After: text data bss dec hex filename 3184548 280792 8960 3474300 35037c _install/lib64/libvulkan_intel.so Reviewed-by: Lionel Landwerlin <[email protected]>
* Revert "anv: Stop generating weak references for instance entrypoints"Jason Ekstrand2018-10-181-0/+13
| | | | | | This reverts commit 00bb42105d6edf6e432c0e3712ffb9d3eb0aece4. It was not as well thought out as I had intended and broke the build when VK_KHR_display is disabled in the build.
* vulkan/wsi: Use VK_EXT_pci_bus_info for DRM fd matchingJason Ekstrand2018-10-182-5/+3
| | | | | | | | This lets us avoid passing the DRM fd around all over the place and gets us closer to layer utopia. Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* anv: Stop generating weak references for instance entrypointsJason Ekstrand2018-10-181-13/+0
| | | | | | | | | We don't need weak references to instance entrypoints because we never have more than one of each so we don't need the NULL fall-back. This also helps us avoid forgetting things because we now get link errors for missing instance entrypoints. Reviewed-by: Lionel Landwerlin <[email protected]>
* vulkan/wsi: Implement GetPhysicalDevicePresentRectanglesKHRJason Ekstrand2018-10-181-0/+14
| | | | | | | | | | | | | | | | | | This got missed during 1.1 enabling because it was defined as an interaction between device groups and WSI and it wasn't obvious it was in the delta. The idea behind it is that it's supposed to provide a hint to the application in a multi-GPU setup to indicate which regions of the screen are being scanned out by which GPU so a multi-device split-screen rendering application can render each part of the screen on the GPU that will be presenting it and avoid extra bus traffic between GPUs. On a single-GPU setup or one which doesn't support this present mode, we need to do something. We choose to return the window size (or a max-size rect) if the compositor, X server, or crtc is associated with the given physical device and zero rectangles otherwise. Reviewed-by: Lionel Landwerlin <[email protected]>
* vulkan/wsi: Store the instance allocator in wsi_deviceJason Ekstrand2018-10-182-3/+0
| | | | | | | | | | | | We already have wsi_device and we know the instance allocator at wsi_device_init time so there's no need to pass it into the physical device queries. This also fixes a memory allocation domain bug that can occur if CreateSwapchain gets called prior to any queries (not likely) in which case the cached connection gets allocated off the device instead of the instance. Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* vulkan: Add VK_EXT_calibrated_timestamps extension (radv and anv) [v5]Keith Packard2018-10-175-0/+150
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Offers three clocks, device, clock monotonic and clock monotonic raw. Could use some kernel support to reduce the deviation between clock values. v2: Ensure deviation is at least as big as the GPU time interval. v3: Set device->lost when returning DEVICE_LOST. Use MAX2 and DIV_ROUND_UP instead of open coding these. Delete spurious TIMESTAMP in radv version. Suggested-by: Jason Ekstrand <[email protected]> Suggested-by: Lionel Landwerlin <[email protected]> v4: Add anv_gem_reg_read to anv_gem_stubs.c Suggested-by: Jason Ekstrand <[email protected]> v5: Adjust maxDeviation computation to max(sampled_clock_period) + sample_interval. Suggested-by: Bas Nieuwenhuizen <[email protected]> Suggested-by: Jason Ekstrand <[email protected]> Signed-off-by: Keith Packard <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* intel/compiler/icl: Use invocation id bits 22:16 instead of 23:17Topi Pohjolainen2018-10-171-2/+6
| | | | | | | | | | | | | | Identifier bits in the dispatch header have changed. See Bspec: SINGLE_PATCH Payload: 3D Pipeline Stages - 3D Pipeline Geometry - Hull Shader (HS) Stage IVB+ - Payloads IVB+ Fixes: KHR-GL46.tessellation_shader.tessellation_shader_tc_barriers.barrier_guarded_read_write_calls Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/fs: Add 64-bit int immediate support to dump_instructions()Matt Turner2018-10-162-0/+8
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* anv/skylake: disable ForceThreadDispatchEnableSergii Romantsov2018-10-161-7/+35
| | | | | | | | | | | | | | | | On Skylake enabling of ForceThreadDispatchEnable causes gpu-hang. -v2: enabling of ForceThreadDispatchEnable is only for gen8, for gen9 and higher reverted enabling of PixelShaderHasUAV. -v3 (Jason Ekstrand): Rework the comments a bit. CC: Jason Ekstrand <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107941 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107760 Fixes: 79270d2140ec (anv: Stop setting 3DSTATE_PS_EXTRA::PixelShaderHasUAV) Signed-off-by: Sergii Romantsov <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: Implement VK_EXT_pci_bus_infoLionel Landwerlin2018-10-163-5/+26
| | | | | | | | Even though the Intel GPU are always at the same PCI location, all the info we need is already provided by libdrm. Let's be future proof. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel: disable FS IR validation in release mode.Kenneth Graunke2018-10-151-0/+2
| | | | | | We probably don't need to iterate, fprintf, and abort in release mode. Reviewed-by: Matt Turner <[email protected]>
* intel/nir, freedreno/ir3: Use the separated dead write vars passCaio Marcelo de Oliveira Filho2018-10-151-0/+1
| | | | | | | No changes to shader-db for intel. No changes to shader-db expected for freedreno. Reviewed-by: Jason Ekstrand <[email protected]>
* anv: Don't advertise ASTC support on BSWJason Ekstrand2018-10-151-0/+8
| | | | | Tested-by: Mark Janes <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* anv: Split dispatch tables into device and instanceJason Ekstrand2018-10-153-91/+230
| | | | | | | | | | | | | | | | | | | | There's no reason why we need generate trampoline functions for instance functions or carry N copies of the instance dispatch table around for every hardware generation. Splitting the tables and being more conservative shaves about 34K off .text and about 4K off .data when built with clang. Before splitting dispatch tables: text data bss dec hex filename 3224305 286216 8960 3519481 35b3f9 _install/lib64/libvulkan_intel.so After splitting dispatch tables: text data bss dec hex filename 3190325 282232 8960 3481517 351fad _install/lib64/libvulkan_intel.so Reviewed-by: Lionel Landwerlin <[email protected]>
* anv/android: we need git_sha1.h in include pathsTapani Pälli2018-10-121-0/+1
| | | | | | Fixes: e4538b9 "anv: Implement VK_KHR_driver_properties" Signed-off-by: Tapani Pälli <[email protected]> Acked-by: Eric Engestrom <[email protected]>
* anv: Clear WM_HZ_OP overrides in init_device_stateNanley Chery2018-10-111-0/+10
| | | | | | | | | | | | | | | | | | | | This is basically a port of commit, 3ade766684933ac84e41634429fb693f85353c11 ("i965: Disable 3DSTATE_WM_HZ_OP fields.") The BDW+ docs describe how to use the 3DSTATE_WM_HZ_OP instruction in the section titled, "Optimized Depth Buffer Clear and/or Stencil Buffer Clear." It mentions that the packet overrides GPU state for the clear operation and needs to be reset to 0s to clear the overrides. Depending on the kernel, we may not get a context with the GPU state for this packet zeroed. Do it ourselves just in case. Prevents a number of GPU hangs when running crucible on ICL. I tried to get the exact number of hangs that occurs without this patch, but was unsuccessful. The test machine became unresponsive before completing the full run. Reviewed-by: Kenneth Graunke <[email protected]>
* anv/gen9+: Initialize new fields in STATE_BASE_ADDRESSJordan Justen2018-10-111-0/+12
| | | | | | Ref: 263b584d5e4 "i965/skl: Emit extra zeros in STATE_BASE_ADDRESS on Skylake." Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/vec4: Fix nir_op_b2[fi] with 64-bit resultJason Ekstrand2018-10-111-1/+6
| | | | | | | | | This is valid NIR but you can't actually hit this case today. GLSL IR doesn't have a bool to double opcode; it does f2d(b2f(x)). In SPIR-V we don't have any to/from bool conversion opcodes at all. However, the next commit will make us start generating it so we should be ready. Reviewed-by: Ian Romanick <[email protected]>
* intel/fs: Fix nir_op_b2[fi] with 64-bit result on Gen8 LP and Gen9 LPJason Ekstrand2018-10-111-5/+5
| | | | | | | | | | | | | | | | | | | | | | Several of the Atom GPUs have additional restrictions on alignment when moving < 64-bit source to a 64-bit destination. All of the nir_op_*2*64 code generation paths respected this, but nir_op_b2[fi] did not. Previous to commit a68dd47b911 it was not possible to generate such an instruction from the GLSL path. It may have been possible from SPIR-V, but it's not clear. The aforementioned patch converts a 64-bit nir_op_fsign into a sequence of operations including a nir_op_b2f with a 64-bit result. This "just works" everywhere except these Atom parts. This problem was not detected during normal CI testing because the Atom parts are not included in developer builds. v2 (idr): Make the patch compile, and make some cosmetic changes. Add a commit message. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108319 Fixes: a68dd47b911 "nir/algebraic: Simplify fsat of fsign" Reviewed-by: Ian Romanick <[email protected]>
* intel: Introducing Whiskey Lake platformRodrigo Vivi2018-10-113-1/+3
| | | | | | | | | | | | | | | | | | | Whiskey Lake uses the same gen graphics as Coffe Lake, including some ids that were previously marked as reserved on Coffe Lake, but that now are moved to WHL page. This follows the ids and approach used on kernel's commit b9be78531d27 ("drm/i915/whl: Introducing Whiskey Lake platform") and commit c1c8f6fa731b ("drm/i915: Redefine some Whiskey Lake SKUs") v2: Lionel noticed that GT{1,2,3} on kernel wasn't following spec when looking to number of EUs, so kernel has been updated. Cc: Lionel Landwerlin <[email protected]> Cc: José Roberto de Souza <[email protected]> Cc: Anuj Phogat <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: add missing unlock in error path.Dave Airlie2018-10-111-0/+1
| | | | | | | | | | Not going to matter, but be consistent. Found by coverity Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Fixes: caf41c78c (anv/allocator: Support softpin in the BO cache)
* intel: Don't propagate conditional modifiers if a UD source is negatedJason Ekstrand2018-10-105-0/+50
| | | | | | | | | This fixes a bug uncovered by my NIR integer division by constant optimization series. Fixes: 19f9cb72c8b "i965/fs: Add pass to propagate conditional..." Fixes: 627f94b72e0 "i965/vec4: adding vec4_cmod_propagation..." Reviewed-by: Ian Romanick <[email protected]>
* intel/compiler: Don't handle fsign.satIan Romanick2018-10-092-23/+3
| | | | | | | No shader-db or CI changes on any Intel platform. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Thomas Helland <[email protected]>
* intel: aubinator: Fix memory leaksSagar Ghuge2018-10-041-0/+25
| | | | | Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/decoder: construct correct xml filenameSagar Ghuge2018-10-041-8/+7
| | | | | | | | | | construct correct gen xml filename when we try to load hardware xml description from a given path v2: remove temporary variable (Francesco Ansanelli) Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/decoder: Avoid freeing invalid pointerSagar Ghuge2018-10-041-5/+13
| | | | | | | | | v2: Free ctx.spec if error while reading genxml (Lionel Landwerlin) v3: Handle case where genxml is empty (Lionel Landwerlin) Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/decoder: add gen_spec_init methodSagar Ghuge2018-10-041-16/+35
| | | | | | | | | | Initialize gen_spec instance properly when loading hardware xml description from specifc directory to avoid segmentation fault. v2: correct function definition (Lionel Landwerlin) Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* anv/batch_chain: Don't start a new BO just for BATCH_BUFFER_STARTJason Ekstrand2018-10-031-0/+9
| | | | | | | | | | | | | | Previously, we just went ahead and emitted MI_BATCH_BUFFER_START as normal. If we are near enough to the end, this can cause us to start a new BO just for the MI_BATCH_BUFFER_START which messes up chaining. We always reserve enough space at the end for an MI_BATCH_BUFFER_START so we can just increment cmd_buffer->batch.end prior to emitting the command. Fixes: a0b133286a3 "anv/batch_chain: Simplify secondary batch return..." Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107926 Tested-by: Alex Smith <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: Use separate MOCS settings for external BOsJason Ekstrand2018-10-0312-38/+80
| | | | | | | | | | | | | | | | | | | On Broadwell and above, we have to use different MOCS settings to allow the kernel to take over and disable caching when needed for external buffers. On Broadwell, this is especially important because the kernel can't disable eLLC so we have to do it in userspace. We very badly don't want to do that on everything so we need separate MOCS for external and internal BOs. In order to do this, we add an anv-specific BO flag for "external" and use that to distinguish between buffers which may be shared with other processes and/or display and those which are entirely internal. That, together with an anv_mocs_for_bo helper lets us choose the right MOCS settings for each BO use. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99507 Cc: [email protected] Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: Ensure discreteQueuePriorities is at least 2Gabriel Majeri2018-10-031-1/+1
| | | | | | | This is the minimum value according to the spec. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* anv: suppress warning about unhandled image layoutEric Engestrom2018-10-021-0/+3
| | | | | | | | | Let's just be explicit that VK_NV_shading_rate_image is not supported. Suggested-by: Jason Ekstrand <[email protected]> Fixes: 6ee17091708a41c4aa81a "vulkan: Update the XML and headers to 1.1.86" Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/fs: Fix a typo in need_matching_subreg_offsetJason Ekstrand2018-10-021-1/+1
| | | | | | | | | This fixes a bunch of Vulkan subgroup tests on little core platforms. Fixes: 4150920b95 "intel/fs: Add a helper for emitting scan operations" Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Tested-by: Mark Janes <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: Implement VK_KHR_driver_propertiesJason Ekstrand2018-10-012-0/+24
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* anv: If softpin is supported, use it with the hiz clear value boJordan Justen2018-09-261-0/+9
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* anv: s/batch/value_bo/ on anv_device_init_hiz_clear_batchJordan Justen2018-09-261-2/+2
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/isl: Add a unit suffixes to some struct fields and variablesJason Ekstrand2018-09-2613-126/+127
| | | | | | | | | | | | | I was about to make the claim to someone that every field in isl_surf is either an enum or has explicit units. Then I looked at isl_surf and discovered this claim was wrong. We should fix that. This commit does a few refactors: * Add _B suffixes to some struct fields * Add _B to some variables and parameters * Rename row_pitch_tiles -> row_pitch_tl Reviewed-by: Nanley Chery <[email protected]>
* intel/compiler: Export TCS passthrough creationCaio Marcelo de Oliveira Filho2018-09-252-0/+86
| | | | | | | Move create_passthrough_tcs() from i965 so can be used in other contexts. Acked-by: Jason Ekstrand <[email protected]>
* intel/compiler/icl: Use barrier id bits 24:30 instead of 24:27,31Topi Pohjolainen2018-09-251-3/+13
| | | | | | | Fixes gpu hangs with Carchase and Manhattan. Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* intel/icl: Fix URB size for different SKUsAnuj Phogat2018-09-211-14/+29
| | | | | | | Different ICL SKUs have different URB sizes. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
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