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* blorp: Properly handle Z24X8 blits.Kenneth Graunke2018-08-112-12/+11
| | | | | | | | | | | | | | | | | | | One of the reasons we didn't notice that R24_UNORM_X8_TYPELESS destinations were broken was that an earlier layer was swapping it out for B8G8R8A8_UNORM. That made Z24X8 -> Z24X8 blits work. However, R32_FLOAT -> R24_UNORM_X8_TYPELESS was still totally broken. The old code only considered one format at a time, without thinking that format conversion may need to occur. This patch moves the translation out to a place where it can consider both formats. If both are Z24X8, we continue using B8G8R8A8_UNORM to avoid having to do shader math workarounds. If we have a Z24X8 destination, but a non-matching source, we use our shader hacks to actually render to it properly. Fixes: 804856fa5735164cc0733ad0ea62adad39b00ae2 (intel/blorp: Handle more exotic destination formats) Reviewed-by: Jason Ekstrand <[email protected]>
* blorp: Don't try to use R32_UNORM for R24_UNORM_X8_TYPELESS rendering.Kenneth Graunke2018-08-111-5/+5
| | | | | | | | | | | | | The hardware doesn't support rendering to R24_UNORM_X8_TYPELESS, so Jason decided to fake it with a bit of shader math and R32_UNORM RTs. The only problem is that R32_UNORM isn't renderable either...so we've just traded one bad format for another. This patch makes us use R32_UINT instead. Fixes: 804856fa5735164cc0733ad0ea62adad39b00ae2 (intel/blorp: Handle more exotic destination formats) Reviewed-by: Jason Ekstrand <[email protected]>
* intel: Switch the order of the 2x MSAA sample positionsJason Ekstrand2018-08-112-5/+15
| | | | | | | | The Vulkan 1.1.82 spec flipped the order to better match D3D. Cc: [email protected] Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* meson: Build with Python 3Mathieu Bridon2018-08-104-10/+10
| | | | | | | | | | | | Now that all the build scripts are compatible with both Python 2 and 3, we can flip the switch and tell Meson to use the latter. Since Meson already depends on Python 3 anyway, this means we don't need two different Python stacks to build Mesa. Signed-off-by: Mathieu Bridon <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* intel: Fix SIMD16 unaligned payload GRF reads on Gen4-5.Kenneth Graunke2018-08-091-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the SIMD16 Gen4-5 fragment shader payload contains source depth (g2-3), destination stencil (g4), and destination depth (g5-6), the single register of stencil makes the destination depth unaligned. We were generating this instruction in the RT write payload setup: mov(16) m14<1>F g5<8,8,1>F { align1 compr }; which is illegal, instructions with a source region spanning more than one register need to be aligned to even registers. This is because the hardware implicitly does (nr | 1) instead of (nr + 1) when splitting the compressed instruction into two mov(8)'s. I believe this would cause the hardware to load g5 twice, replicating subspan 0-1's destination depth to subspan 2-3. This showed up as 2x2 artifact blocks in both TIS-100 and Reicast. Normally, we rely on the register allocator to even-align our virtual GRFs. But we don't control the payload, so we need to lower SIMD widths to make it work. To fix this, we teach lower_simd_width about the restriction, and then call it again after lower_load_payload (which is what generates the offending MOV). Fixes: 8aee87fe4cce0a883867df3546db0e0a36908086 (i965: Use SIMD16 instead of SIMD8 on Gen4 when possible.) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107212 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=13728 Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Diego Viola <[email protected]>
* anv: set error in all failure pathsEric Engestrom2018-08-091-1/+3
| | | | | | | | Cc: Jason Ekstrand <[email protected]> Fixes: 5b196f39bddc689742d3 "anv/pipeline: Compile to NIR in compile_graphics" Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/tools: add missing variable initialisationEric Engestrom2018-08-091-1/+1
| | | | | | Fixes: 6a60beba4089315685b8 "intel/tools: Add an error state to aub translator" Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* python: Fix rich comparisonsMathieu Bridon2018-08-071-2/+3
| | | | | | | | | | | | | | Python 3 doesn't call objects __cmp__() methods any more to compare them. Instead, it requires implementing the rich comparison methods explicitly: __eq__(), __ne(), __lt__(), __le__(), __gt__() and __ge__(). Fortunately Python 2 also supports those. This commit only implements the comparison methods which are actually used by the build scripts. Signed-off-by: Mathieu Bridon <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* intel: don't build tools without -Dtools=intelLionel Landwerlin2018-08-072-15/+15
| | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107487 Fixes: 4334196ab325c6w ("intel: tools: simplify meson build") Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* anv: add more swapchain formatsTapani Pälli2018-08-061-5/+11
| | | | | | | | This change helps with some of the dEQP-VK.wsi.android.* tests that try to create swapchain with using such formats. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* intel: tools: simplify meson buildLionel Landwerlin2018-08-041-46/+50
| | | | | | | | Remove the if tools condition and just put it through the install: parameter. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* intel: aubinator: simplify decodingLionel Landwerlin2018-08-041-10/+5
| | | | | | | | | | Since we don't support streaming an aub file, we can drop the decoding status enum. v2: include stdbool (Eric) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* intel: common: add missing stdint includeLionel Landwerlin2018-08-041-0/+2
| | | | Reviewed-by: Eric Engestrom <[email protected]>
* intel: decoder: remove unused variableLionel Landwerlin2018-08-041-2/+0
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* intel: tools: aubwrite: reuse canonical address helperLionel Landwerlin2018-08-041-17/+2
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* intel: aubinator: fix read the context/ringLionel Landwerlin2018-08-041-2/+2
| | | | | | | | | Up to now we've been lucky that the buffer returned was always exactly at the address we requested. Fixes: 144b40db5411 ("intel: aubinator: drop the 1Tb GTT mapping") Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* anv/pipeline: Disable FS dispatch for pointless fragment shadersJason Ekstrand2018-08-031-4/+33
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/tools: add error2aub creation into autotoolsAndres Gomez2018-08-021-1/+23
| | | | | | | | | | | | | | Tarball distribution is done through "make distcheck". We include the meson targets also into autotools so they won't fail when building from the tarball. Fixes: 6a60beba408 ("intel/tools: Add an error state to aub translator") Cc: Jason Ekstrand <[email protected]> Cc: Lionel Landwerlin <[email protected]> Cc: Dylan Baker <[email protected]> Signed-off-by: Andres Gomez <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* anv/pipeline: Do cross-stage linking optimizationsJason Ekstrand2018-08-021-0/+11
| | | | | | | This appears to help the Aztec Ruins benchmark by about 2% on my Kaby Lake gt2 laptop. Reviewed-by: Timothy Arceri <[email protected]>
* anv/pipeline: Pull most of the anv_pipeline_compile_* into common codeJason Ekstrand2018-08-021-215/+92
| | | | | | | | | | This leaves us with a series of little anv_pipeline_compile_* functions which each take a compiler object, a mem_ctx, the stage to compile, and the previous stage for VUE linking purposes. Some of them do interesting things but most are little more than wrappers around brw_compile_*. Reviewed-by: Timothy Arceri <[email protected]>
* anv/pipeline: Add a separate "link" stageJason Ekstrand2018-08-021-128/+193
| | | | | | | | | | | This breaks compilation up a bit into "link" and "compile". In the "link" stage, new anv_pipeline_link_* helpers are called which are responsible for setting up the binding table and doing anything needed to properly link with the next stage in the pipeline if one exists. They are called in reverse order starting with the fragment shader so you can assume linking in later stages is already done. Reviewed-by: Timothy Arceri <[email protected]>
* anv/pipeline: Compile to NIR in compile_graphicsJason Ekstrand2018-08-021-161/+116
| | | | | | This pulls the SPIR-V to NIR step out into common code. Reviewed-by: Timothy Arceri <[email protected]>
* anv/pipeline: Recompile all shaders if any are missing from the cacheJason Ekstrand2018-08-021-4/+37
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* anv/pipeline: Drop anv_pipeline_add_compiled_stageJason Ekstrand2018-08-022-19/+10
| | | | | | | We can set active_stages much more directly and then it's just candy around setting pipeline->stages[stage]. Reviewed-by: Timothy Arceri <[email protected]>
* anv/pipeline: Pull shader compilation out into a helper.Jason Ekstrand2018-08-021-108/+120
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* anv/pipeline: Call anv_pipeline_compile_* in a loopJason Ekstrand2018-08-021-26/+30
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* anv/pipeline: Hash the entire pipeline in one goJason Ekstrand2018-08-021-53/+94
| | | | | | | | | Instead of hashing each stage separately (and TES and TCS together), we hash the entire pipeline. This means we'll get fewer cache hits if they, for instance, re-use the same VS over and over again but it also means we can now safely do cross-stage optimizations. Reviewed-by: Timothy Arceri <[email protected]>
* anv/pipeline: Populate keys up-frontJason Ekstrand2018-08-021-55/+60
| | | | | | | | Instead of having each anv_pipeline_compile_* function populate the shader key, make it part of the anv_pipeline_stage struct and fill it out up-front. Reviewed-by: Timothy Arceri <[email protected]>
* anv/pipline: Add a helper struct for per-stage infoJason Ekstrand2018-08-022-95/+74
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* intel/compiler: Add brw_get_compiler_config_value for disk cacheJordan Justen2018-08-013-1/+41
| | | | | | | | | | | | | | | | | | | During code review, Jason pointed out that: 2b3064c0731 "i965, anv: Use INTEL_DEBUG for disk_cache driver flags" Didn't account for INTEL_SCALER_* environment variables. To fix this, let the compiler return the disk_cache driver flags. Another possible fix would be to pull the INTEL_SCALER_* into INTEL_DEBUG bits, but as we are currently using 41 of 64 bits, I didn't think it was a good use of 4 more of these bits. (5 since INTEL_PRECISE_TRIG needs to be accounted for as well.) Cc: Jason Ekstrand <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Disable shader cache with INTEL_DEBUG=shader_timeJordan Justen2018-08-011-2/+5
| | | | | | | | | | | | | | | | | | | Shader time hard codes an index of the shader time buffer within the gen program. In order to support shader time in the disk shader cache, we'd need to add the shader time index into the program key. This should work, but probably is not worth it for this particular debug feature. Therefore, let's just disable the disk shader cache if the shader time debug feature is used. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106382 Fixes: 96fe36f7acc "i965: Enable disk shader cache by default" Cc: Eero Tamminen <[email protected]> Cc: Kenneth Graunke <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* anv/pipeline: Add populate_tcs/tes_key helpersJason Ekstrand2018-08-011-3/+25
| | | | | | | They don't really do anything interesting, but it's more consistent this way. Reviewed-by: Timothy Arceri <[email protected]>
* anv/pipeline: Rework the parameters to populate_wm_prog_keyJason Ekstrand2018-08-011-22/+24
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* anv/pipeline: More aggressively optimize away color attachmentsJason Ekstrand2018-08-012-5/+14
| | | | | | | | | | Instead of just looking at the number of color attachments, look at which ones are actually used by the subpass. This lets us potentially throw away chunks of the fragment shader. In DXVK, for example, all subpasses have 8 attachments and most are VK_ATTACHMENT_UNUSED so this is very helpful in that case. Reviewed-by: Timothy Arceri <[email protected]>
* anv: Restrict the number of color regions to those actually writtenJason Ekstrand2018-08-011-0/+5
| | | | | | | | | | The back-end compiler emits the number of color writes specified by wm_prog_key::nr_color_regions regardless of what nir_store_outputs we have. Once we've gone through and figured out which render targets actually exist and are written by the shader, we should restrict the key to avoid extra RT write messages. Reviewed-by: Timothy Arceri <[email protected]>
* anv/pipeline: Fix up deref modes if we delete a FS outputJason Ekstrand2018-08-011-0/+5
| | | | | | | | | With the new deref instructions, we have to keep the modes consistent between the derefs and the variables they reference. Since we remove outputs by changing them to local variables, we need to run the fixup pass to fix the modes. Reviewed-by: Timothy Arceri <[email protected]>
* intel/nir: Call nir_lower_io_to_scalar_earlyJason Ekstrand2018-08-011-5/+12
| | | | | | | | | | | | | | | | | Shader-db results on Kaby Lake: total instructions in shared programs: 15166953 -> 15073611 (-0.62%) instructions in affected programs: 2390284 -> 2296942 (-3.91%) helped: 16469 HURT: 505 total loops in shared programs: 4954 -> 4951 (-0.06%) loops in affected programs: 3 -> 0 helped: 3 HURT: 0 Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/nir: Split IO arrays into elementsJason Ekstrand2018-08-011-0/+4
| | | | | | | | | | | | | | | | | The NIR nir_lower_io_arrays_to_elements pass attempts to split I/O variables which are arrays or matrices into a sequence of separate variables. This can help link-time optimization by allowing us to remove varyings at a more granular level. Shader-db results on Kaby Lake: total instructions in shared programs: 15177645 -> 15168494 (-0.06%) instructions in affected programs: 79857 -> 70706 (-11.46%) helped: 392 HURT: 0 Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Flag all slots of a flat input as flatJason Ekstrand2018-08-011-6/+9
| | | | | | | | | | | | | | | | Otherwise, only the first vec4 of a matrix or other complex type will get marked as flat and we'll interpolate the others. This was caught by a dEQP test which started failing because it did a SSO vs. non-SSO comparison. Previously, we did the interpolation wrong consistently in both versions. However, with one of Tim Arceri's NIR linkingpatches, we started splitting the matrix input into vectors at link time in the non-SSO version and it started getting correctly interpolated which didn't match the broken SSO version. As of this commit, they both get correctly interpolated. Fixes: e61cc87c757f8bc "i965/fs: Add a flat_inputs field to prog_data" Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* intel/nir: Use the correct scalar stage for consumers when linkingJason Ekstrand2018-08-011-1/+1
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* intel: tools: aubwrite: split gen[89] from gen10+Lionel Landwerlin2018-08-015-186/+416
| | | | | | | | | | | Gen10+ has an additional bit in MI_BATCH_BUFFER_END to signal the end of the context image. We select the largest size for the context image regardless of the generation. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* python: Explicitly use byte stringsMathieu Bridon2018-08-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | In both Python 2 and 3, zlib.Compress.compress() takes a byte string, and returns a byte string as well. In Python 2, the script was working because: 1. string literalls were byte strings; 2. opening a file in unicode mode, reading from it, then passing the unicode string to compress() would automatically encode to a byte string; On Python 3, the above two points are not valid any more, so: 1. zlib.Compress.compress() refuses the passed unicode string; 2. compressed_data, defined as an empty unicode string literal, can't be concatenated with the byte string returned by compress(); This commit fixes this by explicitly using byte strings where appropriate, so that the script works on both Python 2 and 3. Signed-off-by: Mathieu Bridon <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* python: Open file in binary modeMathieu Bridon2018-08-011-1/+1
| | | | | | | | | | | | | | | | | | The XML parser wants byte strings, not unicode strings. In both Python 2 and 3, opening a file without specifying the mode will open it for reading in text mode ('r'). On Python 2, the read() method of the file object will return byte strings, while on Python 3 it will return unicode strings. Explicitly specifying the binary mode ('rb') makes the behaviour identical in both Python 2 and 3, returning what the XML parser expects. Signed-off-by: Mathieu Bridon <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* python: Better get character ordinalsMathieu Bridon2018-08-011-2/+2
| | | | | | | | | | | | | | | | | In Python 2, iterating over a byte-string yields single-byte strings, and we can pass them to ord() to get the corresponding integer. In Python 3, iterating over a byte-string directly yields those integers. Transforming the byte string into a bytearray gives us a list of the integers corresponding to each byte in the string, removing the need to call ord(). This makes the script compatible with both Python 2 and 3. Signed-off-by: Mathieu Bridon <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* intel/compiler: implement 8-bit constant loadIago Toral Quiroga2018-08-011-0/+5
| | | | | | Fixes VK-GL-CTS CL#2567 Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: add setup_imm_(u)b helpersIago Toral Quiroga2018-08-012-0/+22
| | | | | | | | The hardware doesn't support byte immediates, so similar to setup_imm_df() for doubles, these helpers work by loading the constant value into a VGRF. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/icl: Disable binding table prefetchingTopi Pohjolainen2018-07-271-0/+7
| | | | | | | | | | | | | Gen 11 workarounds table #2056 WABTPPrefetchDisable suggests to disable prefetching of binding tables for ICLLP A0 and B0 steppings. It fixes multiple gpu hangs in ext_framebuffer_multisample* tests on ICLLP B0 h/w. Anuj: Add comments and commit message. Add gen 11 checks in the code. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/compiler: fix lower conversions to account for predicationIago Toral Quiroga2018-07-271-1/+4
| | | | | | | | The pass can create a temporary result for the instruction and then moves from it to the original destination, however, if the original instruction was predicated, the mov has to be predicated as well. Reviewed-by: Jose Maria Casanova Crespo <[email protected]>
* i965: Combine both gl_PatchVerticesIn lowering passes.Kenneth Graunke2018-07-262-4/+2
| | | | | | | | | | | | | | | | | | Until now, we had separate passes for lowering gl_PatchVerticesIn to a statically known constant (for TES inputs when linked against a TCS), and a uniform in the other cases. Annoyingly, one had to be run before nir_lower_system_values, and the other afterward. This simplified the passes, but made life painful for the callers. This patch combines both into a single pass. If you give it a non-zero static count, it uses that. If you give it Mesa state slots, it turns it back into a built-in uniform. Otherwise, it does nothing. This also moves the i965 uniform lowering out to shared code. v2: Make token arrays const. Reviewed-by: Eric Anholt <[email protected]>
* intel/compiler: Delete dead VS intrinsic handling.Kenneth Graunke2018-07-261-12/+4
| | | | | | | These are lowered by brw_nir_lower_vs_inputs(). If they weren't, we would have already hit the unreachable() in emit_system_values_block(). Reviewed-by: Jason Ekstrand <[email protected]>
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