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* anv/allocator: Use util_dynarray for blocks in anv_state_streamJason Ekstrand2020-03-312-38/+22
| | | | | | | | | | | | | | | | | | | | | | When we originally wrote a bunch of the allocation data structures, we re-used the GPU memory for CPU-side data structures. It's a bit more memory efficient and usually ok. However, this has a couple of problems: 1. It makes it MUCH more likely that the GPU will accidentlly stomp CPU-side data structures and cause nearly impossible to debug crashes. 2. With discrete GPUs, the memory will be mapped somehow and that map may be across the BAR so it could have horribly slow CPU access. This is bad for our CPU-side data structures. In the case of anv_state_stream, it also made the data structure massively more complex than it needed to be. Reviewed-by: Lionel Landwerlin <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4336> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4336>
* anv: Account for the header in anv_state_stream_allocJason Ekstrand2020-03-311-2/+3
| | | | | | | | | | | If we have an allocation that's exactly the block size, we end up computing a new block size to allocate that's exactly the block size, add in the header, and then assert fail. When computing the block size, we need to account for the header. Fixes: 955127db937 "anv/allocator: Add support for large stream..." Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4336>
* anv: Set alignments on descriptor and constant loadsJason Ekstrand2020-03-301-0/+3
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4338>
* intel/nir: Run copy-prop and DCE after lower_bool_to_int32Jason Ekstrand2020-03-301-0/+2
| | | | | | | No shader-db impact on ICL with iris. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4338>
* intel: drop unused include directoriesEric Engestrom2020-03-289-29/+29
| | | | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4360> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4360>
* meson: inline `inc_common`Eric Engestrom2020-03-289-29/+29
| | | | | | | | | Let's make it clear what includes are being added everywhere, so that they can be cleaned up. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4360>
* Move compiler.h and imports.h/c from src/mesa/main into src/utilMarek Olšák2020-03-271-1/+1
| | | | | Reviewed-by: Timothy Arceri <[email protected] Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4324>
* intel/perf: store the probed i915-perf versionLionel Landwerlin2020-03-273-1/+22
| | | | | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Acked-by: Tapani Pälli <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]> Reviewed-by: Mark Janes <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4344> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4344>
* intel/perf: document meaning of query fieldLionel Landwerlin2020-03-271-0/+1
| | | | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Acked-by: Tapani Pälli <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]> Reviewed-by: Mark Janes <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4344>
* intel/perf: move mdapi query definitions to their own fileLionel Landwerlin2020-03-275-346/+388
| | | | | | | | | | | Where they belong. Signed-off-by: Lionel Landwerlin <[email protected]> Acked-by: Jason Ekstrand <[email protected]> Acked-by: Tapani Pälli <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]> Reviewed-by: Mark Janes <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4344>
* intel/perf: break GL query stuff awayLionel Landwerlin2020-03-276-1596/+1682
| | | | | | | | | | | | | | This stuff is somewhat specific to the GL extension & drivers. On Vulkan we won't use this, it also made a rather large file. v2: Fix Android build (Lionel) Signed-off-by: Lionel Landwerlin <[email protected]> Acked-by: Jason Ekstrand <[email protected]> Acked-by: Tapani Pälli <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]> Reviewed-by: Mark Janes <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4344>
* intel/perf: move register definition to special fileLionel Landwerlin2020-03-272-19/+8
| | | | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Acked-by: Tapani Pälli <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]> Reviewed-by: Mark Janes <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4344>
* intel/fs/gen12: Fix interaction of SWSB dependency combination with EU ↵Francisco Jerez2020-03-261-10/+11
| | | | | | | | | | | | | | | | | fusion workaround. This has been reported to fix a hang in Shadow of Mordor on Gen12. One of its compute shaders seems to cause an in-order exec_all dependency to be merged into an out-of-order SET dependency slot, which would prevent us from baking the SET dependency into the parent instruction, leading to an assert failure in emit_inst_dependencies() (Thanks to Rafael for noticing that). Prevent that by avoiding combination of in-order dependencies whenever that would cause a SET dependency to be demoted to a SYNC.NOP instruction. Fixes: e14529ff3262a527 "intel/fs/gen12: Workaround data coherency issues due to broken NoMask control flow." Tested-by: Rafael Antognolli <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/aub_viewer: Fix format specifier for uint64_tDanylo Piliaiev2020-03-261-7/+7
| | | | | | | | | | Use PRIx64 instead of lx for uint64_t Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2692 Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Sagar Ghuge <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4331> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4331>
* util/os_file: extend os_read_file to return the file sizePierre-Eric Pelloux-Prayer2020-03-241-1/+1
| | | | | Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4181>
* intel/dump_gpu: Handle a bunch of getparam in the no-HW caseJason Ekstrand2020-03-241-2/+47
| | | | | | Reviewed-by: Lionel Landwerlin <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4250> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4250>
* intel/dump_gpu: Add an ensure_device_info helperJason Ekstrand2020-03-241-9/+17
| | | | | Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4250>
* anv: Stop fetching the timestamp frequency ourselvesJason Ekstrand2020-03-241-13/+0
| | | | | | | | gen_get_device_info_from_fd fetches the timestamp frequency from the kernel. ANV also carrying code for it is redundant. Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4250>
* intel/tools/aubinator_error_decode: Decode ring buffers from HEAD to TAILD Scott Phillips2020-03-231-5/+43
| | | | | | | | | | | | | | | Capture the HEAD and TAIL register values from the dump and properly index the ring buffer using those. Previously we would decode the ring buffer from the beginning, printing out whatever happened to be there. Also, properly pass the `from_ring` parameter to gen_print_batch() so that decoding doesn't stop once MI_BATCH_BUFFER_END is encoutered. Reviewed-by: Lionel Landwerlin <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4261> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4261>
* intel/tools/aubinator_error_decode: read HW Context before other batchesD Scott Phillips2020-03-231-0/+18
| | | | | | | | | | | The hardware context buffer has state that was set before the batch started. By decoding it first, references to things like Dynamic State Base Address are decodable in the command batches. Reviewed-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4246> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4246>
* anv: Set patch count threshold in 3DSTATE_HSSagar Ghuge2020-03-231-0/+7
| | | | | | | | | Lets specifiy maximum number of patches that will be accumulated before a thread is dispatched. Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3563>
* intel/compiler: Track patch count thresholdSagar Ghuge2020-03-232-0/+33
| | | | | | | | | | | | Return the number of patches to accumulate before an 8_PATCH mode thread is launched. v2: (Kenneth Graunke) - Track patch count threshold instead of input control points. Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3563>
* intel/genxml: Add patch count threshold field on gen12Sagar Ghuge2020-03-231-0/+1
| | | | | | Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3563>
* anv: Only add END_OF_PIPE_SYNC if we actually have AUX_INVALJason Ekstrand2020-03-191-1/+1
| | | | | | | | Fixes: 43dc842cb91c "anv: Wait for the GPU to be idle before..." Reviewed-by: Rafael Antognolli <[email protected]> Reviewed-by: D Scott Phillips <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4234> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4234>
* intel/iris: Always initialize CCS to 0Jason Ekstrand2020-03-191-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, we were initializing the CCS to 0xFF for MCS+CCS due to a misunderstanding of the following lines in the bspec: The following are the general SW requirements for MCS buffer clear functionality: ... - If Software wants to enable Color Compression without Fast clear, Software needs to initialize MCS with zeros. - Lossless compression and CCS initialized to all F (using HW Fast Clear or SW direct Clear) on the same surface is not supported. The first line does not refer to the CCS as the comment author supposed but refers to the MCS as the comment says. It means that if you want to use MCS compression without a fast-clear, you should initialize the MCS to 0x00. This is because the value 0x00 in the MCS means "all data is in plane 0" which is a perfectly valid non-fast-clear initialization. It's also the value the MCS should be in if you do a RECTLIST slow-clear where the primitive fully covers each pixel such that the same value is written to all samples. The second line in the above quote seems to imply that CCS fast-clear is incompatible with MCS fast-clear. In particular, MCS+CCS fast-clear uses a 0xff value in the MCS (like on Gen7-11) and leaves the CCS in either the compressed or the pass-through state. Therefore, we should initialize the CCS to 0x00 even for MCS+CCS surfaces. Reviewed-by: Sagar Ghuge<[email protected]> Reviewed-by: Nanley Chery <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4074> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4074>
* isl: drop min row pitch alignment when set by the driverLionel Landwerlin2020-03-191-1/+9
| | | | | | | | | | | | | | | | | | | | | When the caller of the isl_surf_init() specifies a row pitch, do not consider the minimum CCS requirement if it's incompatible with the caller's value. isl_surf_get_ccs_surf() will check that the main surface alignment matches CCS expectations. v2: Simplify checks (Nanley) v3: Add Comment about isl_surf_get_ccs_surf() (Jason) Signed-off-by: Lionel Landwerlin <[email protected]> Cc: <[email protected]> Fixes: a3f6db2c4e92 ("isl: drop CCS row pitch requirement for linear surfaces") Reviewed-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4243> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4243>
* isl: only apply main surface ccs pitch constraint with CCSLionel Landwerlin2020-03-191-1/+2
| | | | | | | | | | | | | | We could be creating a Y-tiled surface that isn't going to use CCS (this could be the case when clearly indicated through modifiers). Don't apply the main surface pitch alignment constraint in that case. v2: Use logical NOT (Sagar) Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: a3f6db2c4e92 ("isl: drop CCS row pitch requirement for linear surfaces") Reviewed-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4243>
* isl: properly filter supported display modifiers on Gen9+Lionel Landwerlin2020-03-191-3/+13
| | | | | | | | | | | | Y tiling is supported for display on Gen9+ so don't filter it from the possible flags. v2: Drop Yf from display supported tilings on Gen12+ (Jason) Signed-off-by: Lionel Landwerlin <[email protected]> Cc: <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4243>
* isl: implement linear tiling row pitch requirement for displayLionel Landwerlin2020-03-191-3/+14
| | | | | | | | | | | | | | We're missing a requirement for alignment of row pitch for the display HW. In linear tiling, the row pitch must be a 64bytes aligned. v2: Use correct formula to align to 64bytes (Chad) v3: Matching {} (Jason) Signed-off-by: Lionel Landwerlin <[email protected]> Cc: <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4243>
* anv: Swizzle fast-clear valuesJason Ekstrand2020-03-183-9/+19
| | | | | | | | | | | | | | | | | | | Starting with Gen12, we can fast-clear a lot more surface formats and we are suddenly in the position of having to fast-clear surfaces with formats with an implicit swizzle such as VK_FORMAT_R4G4B4A4_UNORM_PACK16 which is represented as ISL_FORMAT_A4B4G4R4 with a BGRA swizzle. In order for blorp to do the fast-clear color conversion for us, it needs a properly swizzled color. This fixes the following Vulkan CTS groups on TGL: - dEQP-VK.pipeline.blend.format.b4g4r4a4_unorm_pack16.* - dEQP-VK.api.image_clearing.core.clear_color_image.*.b4g4r4a4* Cc: [email protected] Reviewed-by: Lionel Landwerlin <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4218> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4218>
* intel/blorp: Add support for swizzling fast-clear colorsJason Ekstrand2020-03-183-4/+12
| | | | | | Cc: [email protected] Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4218>
* anv: Use isl_drm_modifier_get_default_aux_state()Chad Versace2020-03-181-18/+21
| | | | | | | | | | Use it in anv_layout_to_aux_state(). Refactor only. No change in behavior. Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3881> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3881>
* intel/isl: Don't align linear images to 64K on Gen12+Jason Ekstrand2020-03-181-3/+12
| | | | | | Reviewed-by: Lionel Landwerlin <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4048> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4048>
* intel/decoder: don't consider header fields past dword0Lionel Landwerlin2020-03-181-2/+4
| | | | | | | | | v2: use ULL Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Danylo Piliaiev <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4134> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4134>
* anv: Do an end-of-pipe sync before updating AUX table entriesJason Ekstrand2020-03-171-1/+1
| | | | | | | | | | | | We've found in GL that an actual end-of-pipe sync is required before invalidating the aux tables and that a simple CS stall is insufficient. If we're about to modify the actual AUX table entries from the GPU, we should definitely make sure it's stopped dead before we do so. Cc: [email protected] Reviewed-by: Rafael Antognolli <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4206> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4206>
* intel/blorp: Plumb the stage through blorp upload_shaderCaio Marcelo de Oliveira Filho2020-03-175-12/+12
| | | | | | | | | | Vulkan uses that for its own upload function -- even though for BLORP it doesn't really currently care. Neither Iris and i965 makes use of it at the moment. Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4170> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4170>
* anv: Push UBO ranges relative to the start of the bindingJason Ekstrand2020-03-162-12/+16
| | | | | | | | | | | | | | | | | There was a disconnect between anv_nir_compute_push_layout and the code which sets up the push_ubo_sizes array. The NIR code we emit checks relative to the start of the bound UBO range so that, if we end up with a vector which straddles the start of the push range, we can perform the bounds check without risking overflow issues. The code which sets up the push_ubo_sizes, on the other hand, assumed it was relative to the start of the push range. Somehow, this didn't get get caught by any of the available tests. Fixes: e03f9652801 "anv: Bounds-check pushed UBOs when ..." Closes: #2623 Reviewed-by: Lionel Landwerlin <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4195> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4195>
* anv: Fix the comparison in an assertJason Ekstrand2020-03-161-1/+1
| | | | | | Fixes: e03f9652801 "anv: Bounds-check pushed UBOs when ..." Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4195>
* isl: allow compression for storage images on gen12+Tapani Pälli2020-03-161-1/+4
| | | | | | | | | This is done to be able to use ISL_AUX_USAGE_CCS_E with images. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4080>
* intel/compiler: detect if atomic load store operations are usedTapani Pälli2020-03-164-3/+10
| | | | | | | | | Patch adds a new arg and modifies existing calls from i965, anv pass NULL but iris stores this information for later use. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4080>
* isl: Avoid EXPECT_DEATH in unit testsMatt Turner2020-03-134-46/+61
| | | | | | | | | | | | | | | | | | | | | EXPECT_DEATH works by forking the process and letting the forked process fail with an assertion. This process is evidently incredibly expensive, taking ~30 seconds to run the whole isl_aux_info_test on a 2.8GHz Skylake. Annoyingly all of the (expected) assertion failures also leaves lots of messages in dmesg and potentially generates lots of coredumps. Instead, avoid the expense of fork/exec by redefining assert() and unreachable() in the code we're testing to return a unit-test-only value. With this patch, the test takes ~1ms. Also, while modifying the EXPECT_EQ() calls, reverse the arguments so that the expected value comes first, as is intended. Otherwise gtest failure messages don't make much sense. Fixes: https://gitlab.freedesktop.org/mesa/mesa/issues/2567 Reviewed-by: Nanley Chery <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4174> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4174>
* anv: Dump push ranges via VK_KHR_pipeline_executable_propertiesJason Ekstrand2020-03-131-0/+50
| | | | | | Reviewed-by: Lionel Landwerlin <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4173> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4173>
* anv: Remove duplicate code in anv_cmd_buffer_bind_descriptor_setCaio Marcelo de Oliveira Filho2020-03-121-14/+20
| | | | | | | | Also use a single condition statement instead of two. Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4040> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4040>
* anv: Reduce compute pipeline batch_data sizeCaio Marcelo de Oliveira Filho2020-03-123-5/+7
| | | | | | | | | The batch associated with the compute pipeline only needs room for a MEDIA_VFE_STATE. So this patch moves the batch_data to each pipeline struct and cap the one in compute pipeline. Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4040>
* anv: Split graphics and compute bits from anv_pipelineCaio Marcelo de Oliveira Filho2020-03-127-236/+275
| | | | | | | | | Add two new structs that use the anv_pipeline as base. Changed all functions that work on a specific pipeline to use the corresponding struct. Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4040>
* anv: Use a separate field in the pipeline for compute shaderCaio Marcelo de Oliveira Filho2020-03-125-20/+42
| | | | | | | | This is a preparation for splitting the compute and graphics pipelines into separate structs. Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4040>
* anv: Decouple flush_descriptor_sets() from pipeline structCaio Marcelo de Oliveira Filho2020-03-121-23/+45
| | | | | | | | | | | | | Explicitly pass the active stages and the array (and size) of shaders to be processed. This will make easy to store only the shaders needed for each pipeline. The active stages can be identified by a non-NULL shader in the shaders array, so stop using it and keep track of the flushed stages as iteration happens. Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4040>
* anv: Decouple flush_descriptor_sets() helpers from pipeline structCaio Marcelo de Oliveira Filho2020-03-121-20/+19
| | | | | | | | | | Pass the `anv_shader_bin *` instead of expecting the helpers to peek into the pipeline struct. Also reach for the device from the cmd_buffer instead of the pipeline. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4040>
* anv: Remove redundant check in flush_descriptor_sets() helpersCaio Marcelo de Oliveira Filho2020-03-121-10/+0
| | | | | | | | These helpers are only called for stages that are active, so the code for a non-active stage is never executed. Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4040>
* anv: Pass the right pipe_state to flush_descriptor_sets()Caio Marcelo de Oliveira Filho2020-03-121-33/+13
| | | | | | | | | | | The caller has this information, so pass directly instead of making each helper function call figure that one out. Also, since we can reach the pipeline from pipe_state, drop that parameter from the function. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4040>
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