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path: root/src/intel/vulkan/gen7_cmd_buffer.c
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* anv/image: Add an aspects fieldJason Ekstrand2016-05-171-3/+2
| | | | | This makes several checks easier and allows us to avoid calling anv_format_for_vk_format in a number of cases.
* anv: fix warnings in release buildGrazvydas Ignotas2016-04-251-1/+1
| | | | | | | | | Mark variables MAYBE_UNUSED to avoid unused-but-set-variable warnings in release build. Signed-off-by: Grazvydas Ignotas <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* anv: s/anv_batch_emit_blk/anv_batch_emit/Jason Ekstrand2016-04-201-20/+19
| | | | Acked-by: Kristian Høgsberg <[email protected]>
* anv/gen7_cmd_buffer: Use the new emit macroJason Ekstrand2016-04-201-52/+70
| | | | Acked-by: Kristian Høgsberg <[email protected]>
* anv: Remove default scissor and viewport conceptsNanley Chery2016-04-131-22/+4
| | | | | | | | | | | | | Users should never provide a scissor or viewport count of 0 because they are required to set such state in a graphics pipeline. This behavior was previously only used in Meta, which actually just disables those hardware operations at pipeline creation time. Kristian noticed that the current assignment of viewport count reduces the number of viewport uploads, so it is not removed. Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Kristian Høgsberg Kristensen <[email protected]>
* anv: Invalidate state cache before L3 partitioning set-up.Jordan Justen2016-03-281-0/+1
| | | | | | Port 10d84ba9f084174a1e8e7639dfb05dd855ba86e8 to anv. Signed-off-by: Jordan Justen <[email protected]>
* anv: Fix cache pollution race during L3 partitioning set-up.Jordan Justen2016-03-281-10/+26
| | | | | | Port 0aa4f99f562a05880a779707cbcd46be459863bf to anv. Signed-off-by: Jordan Justen <[email protected]>
* anv: Use genxml register support for L3 Cache configJordan Justen2016-03-251-21/+32
| | | | | | | The programming of the L3 Cache registers should match the previous manually packed LRI values. Signed-off-by: Jordan Justen <[email protected]>
* anv/genX: Add flush_pipeline_select_gpgpuJordan Justen2016-03-121-5/+1
| | | | Signed-off-by: Jordan Justen <[email protected]>
* anv/cmd_buffer: Pull the core of flush_state into genX_cmd_bufferJason Ekstrand2016-03-081-144/+3
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* anv/cmd_buffer: Split flush_state into two functionsJason Ekstrand2016-03-081-1/+10
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* anv: Store prog data in pipeline cache streamKristian Høgsberg Kristensen2016-03-051-2/+3
| | | | | We have to keep it there for the cache to work, so let's not have an extra copy in struct anv_pipeline too.
* anv/cmd_buffer: Mask stencil reference valuesJason Ekstrand2016-03-041-2/+2
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* anv/pipeline: Set StencilBufferWriteEnable from the pipelineJason Ekstrand2016-03-041-3/+0
| | | | | The hardware docs say that StencilBufferWriteEnable should only be set if StencilTestEnable is set. It seems reasonable to set them together.
* anv/pipeline: Respect pRasterizationState->depthBiasEnableJason Ekstrand2016-03-041-6/+0
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* anv/cmd_buffer: Look at both sides for stencil enableJason Ekstrand2016-03-011-4/+2
| | | | Now it's all consistent with gen9
* anv/cmd_buffer: Clean up stencil state setup on gen7Jason Ekstrand2016-03-011-12/+8
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* anv/cmd_buffer: Dirty push constants when changing pipelines.Jason Ekstrand2016-02-291-0/+11
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* anv/cmd_buffer: Re-emit push constants packets for all stagesJason Ekstrand2016-02-291-12/+12
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* anv/gen7: Enable SLM in L3 cache control registerJordan Justen2016-02-281-0/+62
| | | | | | Port 1983003 to gen7. Signed-off-by: Jordan Justen <[email protected]>
* anv/gen7: Only try to get the depth format the surface has depthJason Ekstrand2016-02-271-1/+4
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* anv: Get rid of GENX_FUNCJason Ekstrand2016-02-201-5/+7
| | | | It was a bad idea.
* anv: Switch over to the macros in genxmlJason Ekstrand2016-02-201-37/+43
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* Move the intel vulkan driver to src/intel/vulkanJason Ekstrand2016-02-181-0/+589