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* intel/isl: Add ASTC HDR to format lists and helpersNanley Chery2017-05-223-2/+58
| | | | | Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* intel/isl/gen6: Fix combined depth stencil alignmentJason Ekstrand2017-05-161-7/+7
| | | | | | | | All combined depth stencil buffers (even those with just stencil) require a 4x4 alignment on Sandy Bridge. The only depth/stencil buffer type that requires 4x2 is separate stencil. Reviewed-by: Chad Versace <[email protected]>
* intel/isl: Refactor gen8_choose_image_alignment_elJason Ekstrand2017-05-161-140/+49
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* intel/isl: Refactor gen6_choose_image_alignment_elJason Ekstrand2017-05-161-18/+14
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* intel/isl: Refactor gen7_choose_image_alignment_elJason Ekstrand2017-05-161-83/+74
| | | | | | | | | | | | | | | The Ivy Bridge PRM provides a nice table that handles most of the alignment cases in one place. For standard color buffers we have a little freedom of choice but for most depth, stencil and compressed it's hard-coded. Chad's original functions split halign and valign apart and implemented them almost entirely based on restrictions and not the table. This makes things way more confusing than they need to be. This commit gets rid of the split and makes us implement the exact table up-front. If our surface isn't one of the ones in the table then we have to make real choices. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* intel/isl/gen7: Use stencil vertical alignment of 8 instead of 4Pohjolainen, Topi2017-05-161-23/+5
| | | | | | | | | | | | | | | | | | | | | The reasoning Chad gave in the comment for choosing a valign of 4 is entirely bunk. The fact that you have to multiply pitch by 2 is completely unrelated to the halign/valign parameters used for texture layout. (Not completely unrelated. W-tiling is just Y-tiling with a bit of extra swizzling which turns 8x8 W-tiled chunks into 16x4 y-tiled chunks so it makes everything easier if miplevels are always aligned to 8x8.) The fact that RENDER_SURFACE_STATE::SurfaceVerticalAlignmet doesn't have a VALIGN_8 option doesn't matter since this is gen7 and you can't do stencil texturing anyway. v2 (Jason Ekstrand): - Delete most of Chad's comment and add a more descriptive commit message. Signed-off-by: Topi Pohjolainen <[email protected]> Cc: "17.0 17.1" <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* isl/format: Update the R16G16B16X16_FLOAT entryNanley Chery2017-04-241-1/+1
| | | | | | | | | | | The section of the PRM mentioned in the code comment above this table says that this format supports the render target write message. Internal documentation says that this format also supports alpha blending. As a side effect, this allows CCS_D buffers to be created for images with this format. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* anv: Use ISL for emitting depth/stencil/hizJason Ekstrand2017-04-102-2/+2
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add support for emitting depth/stencil/hizJason Ekstrand2017-04-104-0/+394
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Use genx_bits.h instead of a hand-rolled tableJason Ekstrand2017-04-071-18/+13
| | | | | | | | This gets rid of one piece of ugliness with the way ISL handles surface emitting surface states. I've never liked that hand-rolled table but it was the best we had at the time. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Refactor and clerify gen8 alignment calculationsJason Ekstrand2017-04-041-15/+49
| | | | | | | | Adding the actual table from the docs makes it clearer exactly what the restrictions are. In particular, it becomes clear that compressed textures ignore the alignment parameters in RENDER_SURFACE_STATE. Reviewed-by: Chad Versace <[email protected]>
* isl: Drop unused isl_surf_init_info::min_pitchChad Versace2017-03-282-13/+3
| | | | | | Reviewed-by: Nanley Chery <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* isl: Let isl_surf_init's caller set the exact row pitch (v2)Chad Versace2017-03-282-1/+19
| | | | | | | | | The caller does so by setting the new field isl_surf_init_info::row_pitch. v2: Validate the requested row_pitch. Reviewed-by: Jason Ekstrand <[email protected]> (v2)
* isl: Validate the calculated row pitch (v45)Chad Versace2017-03-281-6/+64
| | | | | | | | | | | | | | | | | | | | | | | | Validate that isl_surf::row_pitch fits in the below bitfields, if applicable based on isl_surf::usage. RENDER_SURFACE_STATE::SurfacePitch RENDER_SURFACE_STATE::AuxiliarySurfacePitch 3DSTATE_DEPTH_BUFFER::SurfacePitch 3DSTATE_HIER_DEPTH_BUFFER::SurfacePitch v2: -Add a Makefile dependency on generated header genX_bits.h. v3: - Test ISL_SURF_USAGE_STORAGE_BIT too. [for jekstrand] - Drop explicity dependency on generated header. [for emil] v4: - Rebase for new gen_bits_header.py script. - Replace gen_10x with gen_device_info*. v5: - Drop FINISHME for validation of GEN9 1D row pitch. [for jekstrand] - Reformat bit tests. [for jekstrand] Reviewed-by: Jason Ekstrand <[email protected]> (v4)
* genxml: Rename two MCS fields to Auxiliary Surface on gen7Jason Ekstrand2017-03-241-4/+3
| | | | | | This makes gen7 more consistent with gen8+ Reviewed-by: Chad Versace <[email protected]>
* isl: Refactor row pitch calculation (v2)Chad Versace2017-03-211-33/+89
| | | | | | | | | | | | | | | | | The calculations of row_pitch, the row pitch's alignment, surface size, and base_alignment were mixed together. This patch moves the calculation of row_pitch and its alignment to occur before the calculation of surface_size and base_alignment. This simplifies a follow-on patch that adds a new member, 'row_pitch', to struct isl_surf_init_info. v2: - Also extract the row pitch alignment. - More helper functions that will later help validate the row pitch. Reviewed-by: Nanley Chery <[email protected]> (v2) Reviewed-by: Jason Ekstrand <[email protected]> (v2)
* isl: Drop misplaced comment about paddingChad Versace2017-03-211-46/+0
| | | | | | | | | | | | | isl has a giant comment that explains the hardware's padding requirements. (Hint: Cache lines and page faults). But the comment is in the wrong place, in isl_calc_linear_row_pitch(), which is unrelated to padding. The important parts of that comment were copied to isl_apply_surface_padding() long ago. So drop the misplaced comment. Reviewed-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel: Correct the BDW surface state sizeNanley Chery2017-03-201-1/+1
| | | | | | | | | | | The PRMs state that this packet is 16 DWORDS long. Ensure that the last three DWORDS are zeroed as required by the hardware when allocating a null surface state. Cc: <[email protected]> Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Move the back-end compiler to src/intel/compilerJason Ekstrand2017-03-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | Mostly a dummy git mv with a couple of noticable parts: - With the earlier header cleanups, nothing in src/intel depends files from src/mesa/drivers/dri/i965/ - Both Autoconf and Android builds are addressed. Thanks to Mauro and Tapani for the fixups in the latter - brw_util.[ch] is not really compiler specific, so it's moved to i965. v2: - move brw_eu_defines.h instead of brw_defines.h - remove no-longer applicable includes - add missing vulkan/ prefix in the Android build (thanks Tapani) v3: - don't list brw_defines.h in src/intel/Makefile.sources (Jason) - rebase on top of the oa patches [Emil Velikov: commit message, various small fixes througout] Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* isl: document the meaning of the array_len field in isl_viewIago Toral Quiroga2017-03-021-0/+6
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* intel/isl: Apply render target alignment constraints for MCSPohjolainen, Topi2017-02-231-1/+16
| | | | | | | | v2: Instead of having the same block in isl_gen7,8,9.c add it once into isl.c::isl_choose_image_alignment_el() instead. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* intel/isl: add MCS width constraint 16 samplesLionel Landwerlin2017-02-231-0/+10
| | | | | | | | v3 (Jason Ekstrand): Add a comment explaining why Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* intel/isl: Return surface creation success from aux helpersJason Ekstrand2017-02-232-39/+37
| | | | | | | | | The isl_surf_init call that each of these helpers make can, in theory, fail. We should propagate that up to the caller rather than just silently ignoring it. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* isl/state: fix assert on raw buffer surface state minimum sizeSamuel Iglesias Gonsálvez2017-02-231-1/+1
| | | | | | | | | | | | | | | | | | | From IVB PRM, SURFACE_STATE::Height: "For typed buffer and structured buffer surfaces, the number of entries in the buffer ranges from 1 to 2^27 . For raw buffer surfaces, the number of entries in the buffer is the number of bytes which can range from 1 to 2^30." The minimum value is 1, according to the spec. The spec quote was already added into the code by 028f6d8317f00. Fixes crashing tests under: dEQP-VK.robustness.buffer_access.* Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/isl: Add format metadata for typed reads/writesJason Ekstrand2017-02-142-251/+291
| | | | | | | | This adds two columns to the format table as well as two helpers for determining whether or not a given format is supported for typed reads and writes. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/isl: Add a better comment for format_supports_ccs_eJason Ekstrand2017-02-021-0/+6
| | | | | Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* intel/isl: Assert that we don't use CCS for storage imagesJason Ekstrand2017-02-021-0/+6
| | | | | | | | | | I enabled CCS for storage images in the Vulkan driver and ran it through the CTS. It didn't result in any hangs but it demonstrated that the data port cannot handle CCS. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* intel/isl: Add a formats_are_ccs_e_compatible helperJason Ekstrand2017-02-022-0/+35
| | | | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* intel/isl: Add a format_supports_ccs_d helperJason Ekstrand2017-02-022-0/+24
| | | | | | | | | Nothing uses this yet but it serves as a nice bit of documentation that's relatively easy to find. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* intel/isl: Rename supports_lossless_compression to supports_ccs_eJason Ekstrand2017-02-022-6/+6
| | | | | | | | | | | | | The term "lossless compression" could potentially mean multisample color compression, single-sample color compression or HiZ because they are all lossless. The term CCS_E, however, has a very precise meaning; in ISL and is only used to refer to single-sample color compression. It's also much shorter which is nice. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* isl: Add assertions for render target swizzle restrictionsJason Ekstrand2017-02-011-0/+32
| | | | Reviewed-by: Anuj Phogat <[email protected]>
* isl/formats: Only advertise sampling for A4B4G4R4 on BroadwellJason Ekstrand2017-01-311-2/+3
| | | | | | | | | This causes hangs on Broadwell if you try to render to it. I have no idea how we managed to not hit this earlier. Tested-by: Mark Janes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: "13.0 17.0" <[email protected]>
* isl/surface_state: Handle ISL_AUX_USAGE_HIZNanley Chery2017-01-121-0/+29
| | | | | | | v2: Remove redundant x/y offset asserts (Jason Ekstrand) Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* isl: render target cube maps should be handled as 2D images, not cubesIago Toral Quiroga2017-01-091-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes layered rendering Vulkan CTS tests with cube (arrays). We also do this in the GL driver, see this code from gen8_depth_state.c for example: case GL_TEXTURE_CUBE_MAP_ARRAY: case GL_TEXTURE_CUBE_MAP: /* The PRM claims that we should use BRW_SURFACE_CUBE for this * situation, but experiments show that gl_Layer doesn't work when we do * this. So we use BRW_SURFACE_2D, since for rendering purposes this is * equivalent. */ surftype = BRW_SURFACE_2D; depth *= 6; break; So I guess we simply forgot to port this workaround to Vulkan. v2: tweak the conditions so the special case is cube texture sampling rather than anything else (Jason) Fixes: dEQP-VK.geometry.layered.cube* Reviewed-by: Jason Ekstrand <[email protected]>
* isl: fix VA64 support for double and dvecN vertex attributesSamuel Iglesias Gonsálvez2017-01-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | We use *64*_PASSTHRU formats to upload vertex attributes of 64 bits to avoid conversions. From the BDW PRM, Volume 2d, page 586 (VERTEX_ELEMENT_STATE): "When SourceElementFormat is set to one of the *64*_PASSTHRU formats, 64-bit components are stored in the URB without any conversion. In this case, vertex elements must be written as 128 or 256 bits, with VFCOMP_STORE_0 being used to pad the output as required. E.g., if R64_PASSTHRU is used to copy a 64-bit Red component into the URB, Component 1 must be specified as VFCOMP_STORE_0 (with Components 2,3 set to VFCOMP_NOSTORE) in order to output a 128-bit vertex element, or Components 1-3 must be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex element. Likewise, use of R64G64B64_PASSTHRU requires Component 3 to be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex element." v2,v3 (Jason): - Don't delete unused formats. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* isl: Mark A4B4G4R4_UNORM as supported on gen8Jason Ekstrand2017-01-061-1/+4
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Cc: "13.0" <[email protected]>
* isl: Make isl_finishme only warn once per call-siteEmil Velikov2016-11-281-1/+7
| | | | Signed-off-by: Emil Velikov <[email protected]>
* intel/isl: Allow non-2D CCS surfacesJason Ekstrand2016-11-171-2/+2
| | | | | | | | | The CCS calculations in ISL are already correct for 1-D and 3-D CCS surfaces since they have exactly the same layout as 2-D array surfaces (at least on Sky Lake). The only problem was that we weren't passing in the right dimensionality and we weren't passing in the depth. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Rework the asserts and fails in isl_surf_get_ccsJason Ekstrand2016-11-171-2/+7
| | | | | | | There are some invariants such as number of samples on which we should assert. However, most other things should silently return false since they're much easier for isl_surf_get_ccs to check than the caller. We also update the checking to be a bit more complete.
* intel/isl: Add some basic info about RENDER_SURFACE_STATE to isl_deviceJason Ekstrand2016-11-162-0/+30
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* isl: Fix height calculation in isl_msaa_interleaved_scale_px_to_saJordan Justen2016-11-151-1/+1
| | | | | | | | | | | | No known fixed tests, but it looks like a typo from: commit 8ac99eabb6570f0f3c5f7d7da1332a99ce636362 intel/isl: Add a helper for getting the size of an interleaved pixel Cc: "13.0" <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* isl: Only allow Y-tiling for ASTC texturesNanley Chery2016-11-031-0/+6
| | | | | Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* isl/format: Correct ASTC entries of format info tableNanley Chery2016-10-241-28/+42
| | | | | | | | | With the isl_format_supports* helpers, we can now conveniently report support for this format on Cherry View. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92925 Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* isl: use ifndef header guardsEmil Velikov2016-10-147-7/+28
| | | | | Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* isl: make locally used functions staticEmil Velikov2016-10-142-12/+2
| | | | | Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* isl: trivial include-what-you-want cleanupsEmil Velikov2016-10-145-5/+5
| | | | | | | Noticed while skimming through the files. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* isl/gen7: remove unneeded ISL_DEV_GEN checkEmil Velikov2016-10-141-3/+3
| | | | | | | | | | | | The function gen7_format_needs_valign2 has two callers - the gen7 only gen7_choose_valign_el() and isl_gen6_filter_tiling(). The latter of which already guarding the invocation appropriately. To be extra cautious add a couple of asserts alongside the removal of the runtime check. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* isl: prefix non-static API with isl_Emil Velikov2016-10-1411-116/+116
| | | | | | | | The rest of ISL already follows this approach. Be consistent and resolve the final references. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* isl/gen6: correctly check msaa layout samples countEmil Velikov2016-10-141-1/+1
| | | | | | | | | | | Samples == 1 is a valid value, so returning false is plain wrong. Seeming copy/paste typo introduced since day 1. Fixes: afdadec77f5 ("isl: Implement isl_surf_init() for gen4-gen9") Cc: [email protected] Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* isl: Correct a comment in the isl_format enumNanley Chery2016-10-071-1/+1
| | | | | | | | HiZ is not a color surface, but an auxiliary depth surface. Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
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