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* intel/isl: Add isl_aux_usage_has_ccsJason Ekstrand2019-10-171-0/+7
* intel/isl: Add R10G10B10_FLOAT_A2_UNORM formatJordan Justen2019-10-173-0/+3
* intel/isl: Add gen12 depth/stencil surface alignmentsJordan Justen2019-10-174-2/+121
* intel/isl: Select Y-tiling for stencil on gen12Jason Ekstrand2019-10-171-4/+7
* intel/genxml: Remove W-tiling on gen12Jason Ekstrand2019-10-171-0/+3
* intel/genxml,isl: Add gen12 stencil buffer changesJordan Justen2019-10-171-1/+22
* intel/genxml,isl: Add gen12 depth buffer changesJordan Justen2019-10-171-1/+1
* intel/genxml,isl: Add gen12 render surface state changesJordan Justen2019-10-171-2/+10
* intel/isl: set vertical surface alignment on null surfacesLionel Landwerlin2019-10-051-0/+13
* intel/isl: set surface array appropriatelyLionel Landwerlin2019-10-051-1/+1
* intel/isl: Set null surface format to R32_UINTLionel Landwerlin2019-10-051-1/+6
* intel/isl/icl: Use halign 8 instead of 4 hw workaroundAnuj Phogat2019-10-031-8/+21
* isl: Drop WaDisableSamplerL2BypassForTextureCompressedFormats on Gen11Kenneth Graunke2019-09-201-1/+1
* intel/isl: Build gen12 using gen11 code pathsJordan Justen2019-08-283-1/+7
* isl: Don't set UnormPathInColorPipe for integer surfaces.Kenneth Graunke2019-08-261-1/+6
* isl: Drop UnormPathInColorPipe for buffer surfaces.Kenneth Graunke2019-08-261-4/+0
* isl: Enable Unorm Path in Color PipeKenneth Graunke2019-08-151-0/+8
* i965/tiled_memcpy: avoid creating bswap32 if it exists as a macro (e.g. on Fr...Greg V2019-08-081-0/+3
* meson: replace libmesa_util with idep_mesautilEric Engestrom2019-08-031-2/+2
* intel/device: rename gen_get_device_infoMark Janes2019-08-011-3/+3
* tree-wide: replace MAYBE_UNUSED with ASSERTEDEric Engestrom2019-07-311-2/+2
* intel: drop incorrect MAYBE_UNUSEDEric Engestrom2019-07-311-1/+1
* isl/formats: R8G8B8_UNORM_SRGB isn't supported on HSWJason Ekstrand2019-07-291-1/+5
* isl: Don't align phys_level0_sa by block dimensionNanley Chery2019-06-272-31/+19
* intel: Add and use helpers for level0 extentNanley Chery2019-06-271-0/+32
* isl: tag unreachable path as suchEric Engestrom2019-06-201-0/+2
* isl: Mark enum isl_channel_select packed so it becomes 1 byte.Kenneth Graunke2019-06-071-1/+1
* isl: Add restrictions to isl_surf_get_hiz_surf()Nanley Chery2019-05-141-0/+25
* isl: Add restriction and comments to isl_surf_get_ccs_surf()Nanley Chery2019-05-141-1/+17
* isl: Modify restrictions in isl_surf_get_mcs_surf()Nanley Chery2019-05-141-5/+19
* isl: Set ClearColorConversionEnable.Plamena Manolova2019-04-291-0/+21
* delete autotools .gitignore filesEric Engestrom2019-04-292-2/+0
* intel/isl: Resize clear color buffer to full cachelineRafael Antognolli2019-04-241-1/+2
* intel/isl: Add isl_format_has_color_component() function.Rafael Antognolli2019-03-202-0/+25
* isl: Add a swizzle parameter to isl_buffer_fill_state()Kenneth Graunke2019-03-072-4/+9
* isl: the display engine requires 64B alignment for linear surfacesSamuel Iglesias Gonsálvez2019-02-221-0/+8
* isl: remove the cache line size alignment requirementSamuel Iglesias Gonsálvez2019-02-201-14/+0
* drm-uapi: use local files, not system libdrmEric Engestrom2019-02-142-5/+5
* isl: assert that Gen8+ don't have bit6_swizzlingCaio Marcelo de Oliveira Filho2019-02-041-0/+3
* intel/isl: move tiled_memcpy static libs from i965 to islTapani Pälli2019-01-107-1/+1275
* genxml: Consistently use a numeric "MOCS" fieldKenneth Graunke2018-12-141-3/+3
* meson: Add tests to suitesDylan Baker2018-11-201-1/+2
* i965: Correct L8_UNORM_SRGB table entryGert Wollny2018-11-191-1/+1
* intel/isl: Add a unit suffixes to some struct fields and variablesJason Ekstrand2018-09-266-86/+86
* intel/compiler: Use two components for 1D array image sizesJason Ekstrand2018-08-291-6/+6
* isl: Use the view array length for the image sizeJason Ekstrand2018-08-291-2/+5
* intel/isl: Avoid tiling some 16K-wide render targetsNanley Chery2018-08-221-0/+23
* intel: various python cleanupsEric Engestrom2018-08-161-5/+4
* meson: Build with Python 3Mathieu Bridon2018-08-101-1/+1
* intel/isl/gen4: Make depth/stencil buffers Y-TiledNanley Chery2018-07-191-1/+8
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