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* intel/isl: Add support to emit clear value address.Rafael Antognolli2018-04-052-4/+23
| | | | | | | | | | | | | | gen10 can emit the clear color by setting it on a buffer somewhere, and then adding only the address to the surface state. This commit add support for that on isl_surf_fill_state, and if that is requested, skip setting the clear value itself. v2: Add assert to make sure we are at least on gen10. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel: Use Clear Color struct size.Rafael Antognolli2018-04-052-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The size of the clear color struct (expected by the hardware) is 8 dwords (isl_dev.ss.clear_value_state_size here). But we still need to track the size of the clear color, used when memcopying it to/from the state buffer. For that we keep isl_dev.ss.clear_value_size. v4: - Add struct to gen11 too (Jason, Jordan) - Add field for Converted Clear Color to gen11 (Jason) - Add clear_color_state_offset to differentiate from clear_value_offset. - Fix all the places where clear_value_size was used. v5 (Jason): - Split genxml changes to another commit. - Remove unnecessary gen checks. - Bring back missing offset increment to init_fast_clear_color(). v6 (Jason): - On init_fast_clear_color, change: addr.offset += 4 => sdi.Address.offset += i * 4 - Use GEN_GEN instead of GEN_VERSIONx10. [[email protected]: isl_device_init changes] Signed-off-by: Rafael Antognolli <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel: Drop SURFACE_FORMAT enum from genxml.Kenneth Graunke2018-03-051-3/+3
| | | | | | | | | | | We want people to be using ISL_FORMAT_*, rather than the genxml format enumerations. This patch drops 10 separate copies, and drops a bunch of ugly casting. Reviewed-by: Jordan Justen <[email protected]> [[email protected]: Minor changes for rebase] Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* intel/isl: Add isl_format_is_validJordan Justen2018-03-052-0/+10
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* intel: Split gen_device_info out into libintel_devJordan Justen2018-03-055-5/+5
| | | | | | | | | | | | Split out the device info so isl doesn't depend on intel/common. Now it will depend on the new intel/dev device info lib. This will allow the decoder in intel/common to use isl, allowing us to apply Ken's patch that removes the genxml duplication of surface formats. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* isl: Silence unused parameter warnings in __gen_combine_address implementationsIan Romanick2018-03-022-2/+6
| | | | | | | | | | | | | | | | Reduces my build from 1808 warnings to 1772 warnings by silencing 36 instances of things like ../../SOURCE/master/src/intel/isl/isl_emit_depth_stencil.c: In function ‘__gen_combine_address’: ../../SOURCE/master/src/intel/isl/isl_emit_depth_stencil.c:30:29: warning: unused parameter ‘data’ [-Wunused-parameter] __gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta) ^~~~ ../../SOURCE/master/src/intel/isl/isl_emit_depth_stencil.c:30:41: warning: unused parameter ‘loc’ [-Wunused-parameter] __gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta) ^~~ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* isl/i965/fs: SSBO/UBO buffers need size padding if not multiple of 32-bitJose Maria Casanova Crespo2018-02-281-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The surfaces that backup the GPU buffers have a boundary check that considers that access to partial dwords are considered out-of-bounds. For example, buffers with 1,3 16-bit elements has size 2 or 6 and the last two bytes would always be read as 0 or its writting ignored. The introduction of 16-bit types implies that we need to align the size to 4-bytew multiples so that partial dwords could be read/written. Adding an inconditional +2 size to buffers not being multiple of 2 solves this issue for the general cases of UBO or SSBO. But, when unsized arrays of 16-bit elements are used it is not possible to know if the size was padded or not. To solve this issue the implementation calculates the needed size of the buffer surfaces, as suggested by Jason: surface_size = isl_align(buffer_size, 4) + (isl_align(buffer_size, 4) - buffer_size) So when we calculate backwards the buffer_size in the backend we update the resinfo return value with: buffer_size = (surface_size & ~3) - (surface_size & 3) It is also exposed this buffer requirements when robust buffer access is enabled so these buffer sizes recommend being multiple of 4. v2: (Jason Ekstrand) Move padding logic fron anv to isl_surface_state. Move calculus of original size from spirv to driver backend. v3: (Jason Ekstrand) Rename some variables and use a similar expresion when calculating. padding than when obtaining the original buffer size. Avoid use of unnecesary component call at brw_fs_nir. v4: (Jason Ekstrand) Complete comment with buffer size calculus explanation in brw_fs_nir. Reviewed-by: Jason Ekstrand <[email protected]>
* intel/isl: Improve the documentation on get_default_aux_stateJason Ekstrand2018-02-211-4/+20
| | | | Reviewed-by: Chad Versace <[email protected]>
* intel/isl: Add an isl_color_value_is_zero helperJason Ekstrand2018-02-202-0/+23
| | | | | Cc: [email protected] Reviewed-by: Nanley Chery <[email protected]>
* intel/isl/icl: Build and use gen11 surface state emit functionsAnuj Phogat2018-02-153-1/+7
| | | | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* intel/isl/icl: Add the maximum surface size limitAnuj Phogat2018-02-151-1/+5
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* isl: Don't use surface format R32_FLOAT for typed atomic integer operationsAnuj Phogat2018-02-141-1/+8
| | | | | | | | | | | | | | | From Skylake PRM Surface Formats section: "The surface format for the typed atomic integer operations must be R32_UINT or R32_SINT." Fixes an error and a piglit GPU hang in simulation environment. Piglit test: gl45-imageAtomicExchange-float.shader_test Suggested-by: Francisco Jerez <[email protected]> Signed-off-by: Anuj Phogat <[email protected] Reviewed-by: Kenneth Graunke <[email protected]> Cc: "18.0 17.3" <[email protected]>
* intel/isl: Codify AUX operations in an enumJason Ekstrand2018-02-081-25/+49
| | | | | | | | | Right now, we have different entrypoints and enums in blorp for these different operations. This provides us a central enum which we can begin to transition to. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* meson: don't use intermediate variables that are immediately discardedDylan Baker2018-01-111-4/+2
| | | | | | | | | | | | | | | | For things like: loop x = func() list += x end just do: loop list += func() end Acked-by: Eric Engestrom <[email protected]> Signed-off-by: Dylan Baker <[email protected]>
* meson: Use consistent style for testsDylan Baker2018-01-111-8/+9
| | | | | | | Don't use intermediate variables, use consistent whitespace. Acked-by: Eric Engestrom <[email protected]> Signed-off-by: Dylan Baker <[email protected]>
* isl: Don't require VALIGN_2 for R32G32B32_FLOAT on Haswell.Kenneth Graunke2017-12-151-1/+3
| | | | | | | | | | | | | | According to the RENDER_SURFACE_STATE internal documentation, the R32G32B32_FLOAT restriction is marked "IVB" only. We choose to apply it to Ivybridge and Baytrail, but not Haswell. Apparently fixes KHR-GL46.texture_size_promotion.functional on Haswell. Changes these tests from crashing to skipping on Haswell: - KHR-GL46.direct_state_access.textures_storage_multisample_2d_rgb32f - KHR-GL46.direct_state_access.textures_storage_multisample_3d_rgb32f Reviewed-by: Jason Ekstrand <[email protected]>
* intel/isl: Declare private array as static constChad Versace2017-12-041-1/+1
| | | | | | | | It's array isl_drm.c:modifier_info[] . Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* meson: Don't build intel shared components by defaultDylan Baker2017-11-131-3/+0
| | | | | | | | It's a neat idea, and still useful in some cases, but the intel common code is used by i965 and anvil only, this is a little clearer. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* intel/isl: Disable some gen10 CCS_E formats for nowNanley Chery2017-10-311-0/+24
| | | | | | | | | CannonLake additionally supports R11G11B10_FLOAT and four 10-10-10-2 formats with CCS_E. None of these formats fit within the current blorp_copy framework so disable them until support is added. Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* isl: Fix width check in isl_gen7_choose_msaa_layout.Kenneth Graunke2017-10-191-1/+1
| | | | | | | | | | The restriction is supposed to apply if the width *field* is >= 8192, meaning the actual width *value* is >= 8193. The code also incorrectly used == for some reason. Reviewed-by: Juan A. Suarez Romero <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* meson: fix typo in isltournier.elie2017-10-121-1/+1
| | | | | | Signed-off-by: Elie Tournier <[email protected]> Reviewed-by: Antia Puentes <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* isl: fill out layout descriptions for yuv formatsLionel Landwerlin2017-10-061-4/+4
| | | | | | | Some description was missing. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* isl: check whether a format is rgb if colorspace is yuvLionel Landwerlin2017-10-061-0/+2
| | | | | | | Suggested by Chad. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* isl: make format layout channels accessible by indexLionel Landwerlin2017-10-061-9/+12
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel: Always set Cube Face Enables for all surfaces.Kenneth Graunke2017-10-031-8/+6
| | | | | | | | These shouldn't matter for non-cubes, and we always enable them all for cubes, so we may as well set them all the time. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel: Make Cube Face Enable fields consistent across generations.Kenneth Graunke2017-10-031-4/+0
| | | | | | | | I decided to use the one-boolean-per-cube-face approach because it's clearer which bits correspond to which cube face. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* meson: Add build Intel "anv" vulkan driverDylan Baker2017-09-271-0/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows building and installing the Intel "anv" Vulkan driver using meson and ninja, the driver has been tested against the CTS and has seems to pass the same series of tests (they both segfault when the CTS tries to run wayland wsi tests). There are still a mess of TODO, XXX, and FIXME comments in here. Those are mostly for meson bugs I'm trying to fix, or for additional things to implement for other drivers/features. I have configured all intermediate libraries and optional tools to not build by default, meaning they will only be built if they're pulled in as a dependency of a target that will actually be installed) this allows us to avoid massive if chains, while ensuring that only the bits that need to be built are. v2: - enable anv, x11, and wayland by default - add configure option to disable valgrind v3: - fix typo in meson_options (Nicholas) v4: - Remove dead code (Eric) - Remove change to generator that was from v0 (Eric) - replace if chain with loop (Eric) - Fix typos (Eric) - define HAVE_DLOPEN for both libdl and builtin dl cases (Eric) v5: - rebase on util string buffer implementation Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]> (v4)
* intel/isl: Add a drm_modifier_get_default_aux_state helperJason Ekstrand2017-09-181-0/+20
| | | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Daniel Stone <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* intel/isl: Mark functions used conditionally as UNUSEDMatt Turner2017-08-291-1/+1
| | | | | | | | The functions we're marking as UNUSED in isl_surface_state.c are used only when compiling for particular generations. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* intel/isl: Explicitly cast between different enumsMatt Turner2017-08-291-8/+9
| | | | | | | | | | | | | Fixes warnings like warning: implicit conversion from enumeration type 'enum isl_format' to different enumeration type 'enum GEN10_SURFACE_FORMAT' [-Wenum-conversion] .SourceElementFormat = ISL_FORMAT_R32_UINT, ^~~~~~~~~~~~~~~~~~~ Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* intel/isl: Remove 'inline' keywordsMatt Turner2017-08-293-4/+4
| | | | | | | | | | | | | | | | | | | Unless you have data, the compiler knows better than you whether a function should be inlined. Unlike all other cases in this series, the removal of the inline keyword from isl_format_has_channel_type actually changes the resulting binary with gcc-6.3.0: text data bss dec hex filename 7831116 346384 420648 8598148 833284 i965_dri.so before 7830716 346384 420648 8597748 8330f4 i965_dri.so after I think this is likely an improvement. No difference in the resulting binary with clang-4.0. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* isl: Add a null surface fill function.Kenneth Graunke2017-08-194-0/+40
| | | | | | | | | | ISL already offers functions to fill out most kinds of SURFACE_STATE, so why not handle null surfaces too? Null surfaces are simple, so we can just take the dimensions, rather than an entirte fill structure. Reviewed-by: Jason Ekstrand <[email protected]>
* intel/isl: Replace switch statements of doom with a macroJason Ekstrand2017-08-171-96/+39
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/isl: Reduce header file duplicationJason Ekstrand2017-08-174-101/+78
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Pretend that CCS modified images are two planesBen Widawsky2017-08-141-0/+6
| | | | | | | | | | | | | | | | v2: move is_aux into if block. (Jason) Use else block instead of goto (Jason) v3: Fix up logic for is_aux (Ben) Fix up size calculations and add FIXME (Ben) v4 (Jason Ekstrand): Use the aux_pitch in the image instead of calculating it Signed-off-by: Ben Widawsky <[email protected]> Acked-by: Daniel Stone <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* intel/isl: Add support for I915_FORMAT_MOD_Y_TILED_CCSJason Ekstrand2017-08-141-0/+7
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* isl: Validate row pitch of stencil surfaces.Kenneth Graunke2017-08-101-2/+7
| | | | | | | | | | | | Also, silence an obnoxious finishme that started occurring for all GL applications which use stencil after the i965 ISL conversion. v2: Check against 3DSTATE_STENCIL_BUFFER's pitch bits when using separate stencil, and 3DSTATE_DEPTH_BUFFER's bits when using combined depth-stencil. Cc: "17.2" <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/isl: Don't align the height of the last array sliceJason Ekstrand2017-08-071-1/+2
| | | | | | | | | | | | | We were calculating the total height of 2D surfaces by multiplying the row pitch by the number of slices. This means that we actually request slightly more space than actually needed since the padding on the last slice is unnecessary. For tiled surfaces this is not likely to make a difference. For linear surfaces, on the other hand, this means we may require additional memory. In particular, this makes the i965 driver reject EGL imports of buffers which do not have this extra padding. Reviewed-by: Jordan Justen <[email protected]> Cc: "17.2" <[email protected]>
* intel/isl: Stop padding surfacesJason Ekstrand2017-08-071-117/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The docs contain a bunch of commentary about the need to pad various surfaces out to multiples of something or other. However, all of those requirements are about avoiding GTT errors due to missing pages when the data port or sampler accesses slightly out-of-bounds. However, because the kernel already fills all the empty space in our GTT with the scratch page, we never have to worry about faulting due to OOB reads. There are two caveats to this: 1) There is some potential for issues with caches here if extra data ends up in a cache we don't expect due to OOB reads. However, because we always trash the entire cache whenever we need to move anything between cache domains, this shouldn't be an issue. 2) There is a potential issue if a surface gets placed at the very top of the GTT by the kernel. In this case, the hardware could potentially end up trying to read past the top of the GTT. If it nicely wraps around at the 48-bit (or 32-bit) boundary, then this shouldn't be an issue thanks to the scratch page. If it doesn't, then we need to come up with something to handle it. Up until some of the GL move to ISL, having the padding code in there just caused us to harmlessly use a bit more memory in Vulkan. However, now that we're using ISL sizes to validate external dma-buf images, these padding requirements are causing us to reject otherwise valid images due to the size of the BO being too small. Acked-by: Kenneth Graunke <[email protected]> Tested-by: Tapani Pälli <[email protected]> Tested-by: Tomasz Figa <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Cc: "17.2" <[email protected]>
* intel/isl: Add some sanity checks for compressed surfacesJason Ekstrand2017-07-221-0/+18
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/isl: Add a helper to get a subimage surfaceJason Ekstrand2017-07-222-0/+64
| | | | | | | We already have a helper for doing this in BLORP, this just moves the logic into ISL where we can share it with other components. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/isl: Add a helper for determining if a color is 0/1Jason Ekstrand2017-07-222-0/+30
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl/format: Add an srgb_to_linear helperJason Ekstrand2017-07-222-1/+53
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl/format: Dedent the template in gen_format_layout.pyJason Ekstrand2017-07-221-58/+57
| | | | | | | This makes it much easier to edit the template and doesn't really dirty the python all that much. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add an aux state for "partial clear"Jason Ekstrand2017-07-221-35/+53
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add surface state clear value informationNanley Chery2017-07-222-0/+13
| | | | | | | | This will be used to load and store clear values from surface state objects. Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/isl: Tighten up restrictions for CCS on gen7Jason Ekstrand2017-07-221-7/+23
| | | | | | | | | | It may technically be possible to enable some sort of fast-clear support for at least the base slice of a 2D array texture on gen7. However, it's not documented to work, we've never tried to do it in GL, and we have no idea what the hardware does if you turn on CCS_D with arrayed rendering. Let's just play it safe and disallow it for now. If someone really cares that much about gen7 performance, they can come along and try to get it working later.
* intel/isl/gen7: Don't allow multisampled surfaces with valign2Topi Pohjolainen2017-07-221-19/+23
| | | | | | | | | | | | | | | | | There is the same constraintg later on as assert in isl_gen7_choose_image_alignment_el() so catch it earlier in order to return error instead of crash. Needed to avoid crashes with piglits on IVB and HSW: arb_internalformat_query2.image_format_compatibility_type pname checks arb_internalformat_query2.all internalformat_<x>_type pname checks arb_internalformat_query2.max dimensions related pname checks arb_copy_image.arb_copy_image-formats --samples=2/4/6/8 arb_texture_float.multisample-fast-clear gl_arb_texture_float Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* intel/isl/gen7: Allow msaa with signed integer formatsTopi Pohjolainen2017-07-221-2/+3
| | | | | | | | | | | | | These formats are already allowed by the i965 GL driver, and the feature seems to work just fine. There are tests for multisampled rendering in piglit: tests/spec/ext_framebuffer_multisample which can be patched to try 16I/32I in addition to GL_RGBA8I. IvyBridge passed all tests with all sample numbers. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* intel/isl/gen7: Allow msaa with 128-bit formatsTopi Pohjolainen2017-07-221-4/+7
| | | | | | | | | | | | | | These formats are already allowed by the i965 GL driver, and the feature seems to work just fine. There are tests for multisampled rendering in piglit: tests/spec/ext_framebuffer_multisample which can be patched to try GL_RGBA16F/32F/16I/16UI/32I/32UI in addition to GL_RGBA/8I. IvyBridge passed all tests with all sample numbers and even with 128-bit formats. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
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