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* intel/isl/gen4: Represent cube maps with 3D layoutTopi Pohjolainen2017-07-201-6/+35
| | | | | | | v2 (Jason): Check for !ISL_SURF_DIM_3D instead of CUBE_BIT. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add i915 to isl_tiling converterTopi Pohjolainen2017-07-202-0/+20
| | | | | | | | v2: s/i915_tiling_to_isl_tiling(/isl_tiling_from_i915_tiling/ Reviewed-by: Daniel Stone <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* intel/isl: Take 3D surfaces into account in image paramsTopi Pohjolainen2017-07-181-2/+6
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add a row_pitch parameter to surf_get_ccs_surfJason Ekstrand2017-07-172-2/+5
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* isl: use 64bit arithmetic to compute sizeLionel Landwerlin2017-07-131-2/+2
| | | | | | | | | If we allow the size to be more than 2^32, then we should compute it in 64bit arithmetic otherwise we might run into overflow issues. CID: 1412892, 1412891 Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* intel/isl: Add a helper to convert tilings from ISL to i915Jason Ekstrand2017-07-122-0/+28
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* intel/isl: Add basic modifier introspectionJason Ekstrand2017-07-122-0/+81
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* Revert "intel/isl: Only create a CCS buffer if the image supports rendering"Nanley Chery2017-07-071-1/+1
| | | | | | | | | This reverts commit 8aaa13467dc289d35dc7900ab9fab9a7689c4178, which was based on an incorrect assumption. Unlike the restriction placed on image views in the Vulkan API, OpenGL allows you to render to texture views whose formats differ from the originals. Bugzilla: https://bugzilla.freedesktop.org/show_bug.cgi?id=101677
* intel/isl: Only create a CCS buffer if the image supports renderingNanley Chery2017-06-261-1/+1
| | | | | | | | v2: Omit the commit message. Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/isl: Limit CCS to one level and layer on gen7Nanley Chery2017-06-261-2/+7
| | | | | | | | | | v2 (Jason Ekstrand): - Remove Vulkan-specific terminology from the commit title. - Replace '== 7' with '<= 7' to hint that this is a new feature on BDW+. Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> (v1) Reviewed-by: Jason Ekstrand <[email protected]>
* intel: compiler/i965: fix is_broxton checksLionel Landwerlin2017-06-201-2/+2
| | | | | | | | | | In 5f2fe9302c is_geminilake was introduced for the differenciate broxton from geminilake. Unfortunately I failed as verifying that is_broxton is throughout the code base to mean Gen9lp. Fixes: 5f2fe9302c ("intel: common: add flag to identify platforms by name") Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/isl/gen6: Allow arrayed stencilTopi Pohjolainen2017-06-171-1/+0
| | | | | | | | Nothing prevents arrayed stencil surfaces even though hardware doesn't support mipmapping. Reviewed-by: Nanley Chery <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add the maximum surface size limitAnuj Phogat2017-06-161-0/+22
| | | | | | | | V2: Use 2^31 bytes (2GB) surface size limit on pre-gen9 and 2^38 bytes for gen9+. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/isl: Use uint64_t to store total surface sizeAnuj Phogat2017-06-162-2/+3
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/isl: Properly set SeparateStencilBufferEnable on gen5-6Jason Ekstrand2017-06-141-3/+10
| | | | | | | On gen5-6, SeparateStencilBufferEnable and HierarchicalDepthBufferEnable come hand in hand and we have to set either both or neither. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965/cnl: Enable CCS_E and RT support for few formatsAnuj Phogat2017-06-091-9/+9
| | | | | | Suggested-by: Jason Ekstrand <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/cnl: Reformat surface_format_info table to accomodate gen10+Anuj Phogat2017-06-091-263/+263
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* i965/cnl: Handle gen10 in switch cases across the driverAnuj Phogat2017-06-091-0/+9
| | | | | | | | | V2: Start using gen10 functions isl_gen10*(), gen10_blorp_exec() gen10_init_atoms() (Jason) Remove Vulkan changes. Do them later in a separate patch. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/cnl: Add gen10 specific function declarationsAnuj Phogat2017-06-091-0/+12
| | | | | | | | | These declarations will help the code start compiling once we wire up the makefiles for gen10. Later patches will start using these functions for gen10. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/isl: Add an enum for describing auxiliary compression stateJason Ekstrand2017-06-071-0/+169
| | | | | | | | | | | | This enum describes all of the states that a auxiliary compressed surface can have. All of the states as well as normative language for referring to each of the compression operations is provided in the truly colossal comment for the new isl_aux_state enum. There is also a diagram showing how surfaces move between the different states. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Nanley Chery <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/miptree: Store fast clear colors in an isl_color_valueJason Ekstrand2017-06-071-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | This commit, out of necessity, makes a number of changes at once: 1) Changes intel_mipmap_tree to store the clear color for both color and depth as an isl_color_value. 2) Changes the depth/stencil emit code to do the format conversion of the depth clear value on Haswell and earlier instead of pulling a uint32_t directly from the miptree. 3) Changes ISL's depth/stencil emit code to perform the format conversion of the depth clear value on Haswell and earlier instead of assuming that the depth value in the float is pre-converted. 4) Changes blorp to pass the depth value through as a float. 5) Changes the Vulkan driver to pass the depth value to blorp as a float rather than a uint. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* intel/isl: Add a helper for getting the byte/tile offset of a subimageJason Ekstrand2017-06-012-0/+60
| | | | | | | | | Frequently, get_image_offset_sa is combined with get_intratile_offset_sa so it makes sense to have a single helper to do both. If the caller doesn't want the intratile offsets, it can simply pass NULL and ISL will assert that they are 0. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Make get_intratile_offset_el take the element size in bitsJason Ekstrand2017-06-012-8/+5
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add a new layout for HiZ and stencil on Sandy BridgeJason Ekstrand2017-06-012-5/+197
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Generate phys_total_el from isl_calc_phys_extentJason Ekstrand2017-06-011-68/+97
| | | | | | | | | | The only surface layout for which slice0 makes any sense is GEN4_2D. Move all of the slice0 stuff into isl_calc_phys_total_extent_el_gen4_2d and make the others trivially return the total size in surface elements. As a side-effect, array_pitch_el_rows is now returned from these helpers as well. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Don't check array pitch for gen4 3D texturesJason Ekstrand2017-06-011-1/+0
| | | | | | Array pitch doesn't matter in this layout. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Refactor to use a phys_total_el extent.Jason Ekstrand2017-06-011-19/+19
| | | | | | | We've already implicitly been using a physical total size in surface elements. This just centralizes things a bit. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add an isl_assert_div helperJason Ekstrand2017-06-011-0/+7
| | | | | | | This is a fairly common operation and it's nice to be able to just call the one little function. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Refactor isl_calc_array_pitch_el_rowsJason Ekstrand2017-06-011-47/+46
| | | | | | | | | | | Over 90% of the function only applies to ISL_DIM_LAYOUT_GEN4_2D anyway so we can just handle the other two as special cases at the top. The two "generic" cases below the switch only apply on gen9 and above and only to 3D or CCS surfaces. This implies that they only apply to surfaces with ISL_DIM_LAYOUT_GEN4_2D. Making them look generic is a lie. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Move isl_calc_array_pitch_el_rows higher upJason Ekstrand2017-06-011-117/+117
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Remove the device parameter from isl_tiling_get_infoJason Ekstrand2017-06-013-28/+14
| | | | | | | | | We were only using it for validating that we don't use Ys/Yf on gen8 and earlier. Removing it from isl_tiling_get_info lets us remove it from a bunch of other things that had no business needing a hardware generation. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add gen4_filter_tilingJason Ekstrand2017-05-263-2/+57
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add support for setting component write disablesJason Ekstrand2017-05-262-0/+26
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add support for gen4 cube maps to get_image_offset_saJason Ekstrand2017-05-261-5/+18
| | | | | | | Gen4 cube maps are a 2-D surface with ISL_DIM_LAYOUT_GEN4_3D which is a bit weird but accurate none the less. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Don't request space for stencil/hiz packets unless neededJason Ekstrand2017-05-261-7/+6
| | | | | | | On Iron Lake, the packets exist but we never emit them so there's no need for us to ask the driver to make batch space for them. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add ASTC HDR to format lists and helpersNanley Chery2017-05-223-2/+58
| | | | | Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* intel/isl/gen6: Fix combined depth stencil alignmentJason Ekstrand2017-05-161-7/+7
| | | | | | | | All combined depth stencil buffers (even those with just stencil) require a 4x4 alignment on Sandy Bridge. The only depth/stencil buffer type that requires 4x2 is separate stencil. Reviewed-by: Chad Versace <[email protected]>
* intel/isl: Refactor gen8_choose_image_alignment_elJason Ekstrand2017-05-161-140/+49
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* intel/isl: Refactor gen6_choose_image_alignment_elJason Ekstrand2017-05-161-18/+14
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* intel/isl: Refactor gen7_choose_image_alignment_elJason Ekstrand2017-05-161-83/+74
| | | | | | | | | | | | | | | The Ivy Bridge PRM provides a nice table that handles most of the alignment cases in one place. For standard color buffers we have a little freedom of choice but for most depth, stencil and compressed it's hard-coded. Chad's original functions split halign and valign apart and implemented them almost entirely based on restrictions and not the table. This makes things way more confusing than they need to be. This commit gets rid of the split and makes us implement the exact table up-front. If our surface isn't one of the ones in the table then we have to make real choices. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* intel/isl/gen7: Use stencil vertical alignment of 8 instead of 4Pohjolainen, Topi2017-05-161-23/+5
| | | | | | | | | | | | | | | | | | | | | The reasoning Chad gave in the comment for choosing a valign of 4 is entirely bunk. The fact that you have to multiply pitch by 2 is completely unrelated to the halign/valign parameters used for texture layout. (Not completely unrelated. W-tiling is just Y-tiling with a bit of extra swizzling which turns 8x8 W-tiled chunks into 16x4 y-tiled chunks so it makes everything easier if miplevels are always aligned to 8x8.) The fact that RENDER_SURFACE_STATE::SurfaceVerticalAlignmet doesn't have a VALIGN_8 option doesn't matter since this is gen7 and you can't do stencil texturing anyway. v2 (Jason Ekstrand): - Delete most of Chad's comment and add a more descriptive commit message. Signed-off-by: Topi Pohjolainen <[email protected]> Cc: "17.0 17.1" <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* isl/format: Update the R16G16B16X16_FLOAT entryNanley Chery2017-04-241-1/+1
| | | | | | | | | | | The section of the PRM mentioned in the code comment above this table says that this format supports the render target write message. Internal documentation says that this format also supports alpha blending. As a side effect, this allows CCS_D buffers to be created for images with this format. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* anv: Use ISL for emitting depth/stencil/hizJason Ekstrand2017-04-102-2/+2
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add support for emitting depth/stencil/hizJason Ekstrand2017-04-104-0/+394
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Use genx_bits.h instead of a hand-rolled tableJason Ekstrand2017-04-071-18/+13
| | | | | | | | This gets rid of one piece of ugliness with the way ISL handles surface emitting surface states. I've never liked that hand-rolled table but it was the best we had at the time. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Refactor and clerify gen8 alignment calculationsJason Ekstrand2017-04-041-15/+49
| | | | | | | | Adding the actual table from the docs makes it clearer exactly what the restrictions are. In particular, it becomes clear that compressed textures ignore the alignment parameters in RENDER_SURFACE_STATE. Reviewed-by: Chad Versace <[email protected]>
* isl: Drop unused isl_surf_init_info::min_pitchChad Versace2017-03-282-13/+3
| | | | | | Reviewed-by: Nanley Chery <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* isl: Let isl_surf_init's caller set the exact row pitch (v2)Chad Versace2017-03-282-1/+19
| | | | | | | | | The caller does so by setting the new field isl_surf_init_info::row_pitch. v2: Validate the requested row_pitch. Reviewed-by: Jason Ekstrand <[email protected]> (v2)
* isl: Validate the calculated row pitch (v45)Chad Versace2017-03-281-6/+64
| | | | | | | | | | | | | | | | | | | | | | | | Validate that isl_surf::row_pitch fits in the below bitfields, if applicable based on isl_surf::usage. RENDER_SURFACE_STATE::SurfacePitch RENDER_SURFACE_STATE::AuxiliarySurfacePitch 3DSTATE_DEPTH_BUFFER::SurfacePitch 3DSTATE_HIER_DEPTH_BUFFER::SurfacePitch v2: -Add a Makefile dependency on generated header genX_bits.h. v3: - Test ISL_SURF_USAGE_STORAGE_BIT too. [for jekstrand] - Drop explicity dependency on generated header. [for emil] v4: - Rebase for new gen_bits_header.py script. - Replace gen_10x with gen_device_info*. v5: - Drop FINISHME for validation of GEN9 1D row pitch. [for jekstrand] - Reformat bit tests. [for jekstrand] Reviewed-by: Jason Ekstrand <[email protected]> (v4)
* genxml: Rename two MCS fields to Auxiliary Surface on gen7Jason Ekstrand2017-03-241-4/+3
| | | | | | This makes gen7 more consistent with gen8+ Reviewed-by: Chad Versace <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-22 23:12:57 +0000