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* i965: Move the back-end compiler to src/intel/compilerJason Ekstrand2017-03-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | Mostly a dummy git mv with a couple of noticable parts: - With the earlier header cleanups, nothing in src/intel depends files from src/mesa/drivers/dri/i965/ - Both Autoconf and Android builds are addressed. Thanks to Mauro and Tapani for the fixups in the latter - brw_util.[ch] is not really compiler specific, so it's moved to i965. v2: - move brw_eu_defines.h instead of brw_defines.h - remove no-longer applicable includes - add missing vulkan/ prefix in the Android build (thanks Tapani) v3: - don't list brw_defines.h in src/intel/Makefile.sources (Jason) - rebase on top of the oa patches [Emil Velikov: commit message, various small fixes througout] Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* isl: document the meaning of the array_len field in isl_viewIago Toral Quiroga2017-03-021-0/+6
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* intel/isl: Apply render target alignment constraints for MCSPohjolainen, Topi2017-02-231-1/+16
| | | | | | | | v2: Instead of having the same block in isl_gen7,8,9.c add it once into isl.c::isl_choose_image_alignment_el() instead. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* intel/isl: add MCS width constraint 16 samplesLionel Landwerlin2017-02-231-0/+10
| | | | | | | | v3 (Jason Ekstrand): Add a comment explaining why Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* intel/isl: Return surface creation success from aux helpersJason Ekstrand2017-02-232-39/+37
| | | | | | | | | The isl_surf_init call that each of these helpers make can, in theory, fail. We should propagate that up to the caller rather than just silently ignoring it. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* isl/state: fix assert on raw buffer surface state minimum sizeSamuel Iglesias Gonsálvez2017-02-231-1/+1
| | | | | | | | | | | | | | | | | | | From IVB PRM, SURFACE_STATE::Height: "For typed buffer and structured buffer surfaces, the number of entries in the buffer ranges from 1 to 2^27 . For raw buffer surfaces, the number of entries in the buffer is the number of bytes which can range from 1 to 2^30." The minimum value is 1, according to the spec. The spec quote was already added into the code by 028f6d8317f00. Fixes crashing tests under: dEQP-VK.robustness.buffer_access.* Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/isl: Add format metadata for typed reads/writesJason Ekstrand2017-02-142-251/+291
| | | | | | | | This adds two columns to the format table as well as two helpers for determining whether or not a given format is supported for typed reads and writes. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/isl: Add a better comment for format_supports_ccs_eJason Ekstrand2017-02-021-0/+6
| | | | | Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* intel/isl: Assert that we don't use CCS for storage imagesJason Ekstrand2017-02-021-0/+6
| | | | | | | | | | I enabled CCS for storage images in the Vulkan driver and ran it through the CTS. It didn't result in any hangs but it demonstrated that the data port cannot handle CCS. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* intel/isl: Add a formats_are_ccs_e_compatible helperJason Ekstrand2017-02-022-0/+35
| | | | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* intel/isl: Add a format_supports_ccs_d helperJason Ekstrand2017-02-022-0/+24
| | | | | | | | | Nothing uses this yet but it serves as a nice bit of documentation that's relatively easy to find. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* intel/isl: Rename supports_lossless_compression to supports_ccs_eJason Ekstrand2017-02-022-6/+6
| | | | | | | | | | | | | The term "lossless compression" could potentially mean multisample color compression, single-sample color compression or HiZ because they are all lossless. The term CCS_E, however, has a very precise meaning; in ISL and is only used to refer to single-sample color compression. It's also much shorter which is nice. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* isl: Add assertions for render target swizzle restrictionsJason Ekstrand2017-02-011-0/+32
| | | | Reviewed-by: Anuj Phogat <[email protected]>
* isl/formats: Only advertise sampling for A4B4G4R4 on BroadwellJason Ekstrand2017-01-311-2/+3
| | | | | | | | | This causes hangs on Broadwell if you try to render to it. I have no idea how we managed to not hit this earlier. Tested-by: Mark Janes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: "13.0 17.0" <[email protected]>
* isl/surface_state: Handle ISL_AUX_USAGE_HIZNanley Chery2017-01-121-0/+29
| | | | | | | v2: Remove redundant x/y offset asserts (Jason Ekstrand) Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* isl: render target cube maps should be handled as 2D images, not cubesIago Toral Quiroga2017-01-091-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes layered rendering Vulkan CTS tests with cube (arrays). We also do this in the GL driver, see this code from gen8_depth_state.c for example: case GL_TEXTURE_CUBE_MAP_ARRAY: case GL_TEXTURE_CUBE_MAP: /* The PRM claims that we should use BRW_SURFACE_CUBE for this * situation, but experiments show that gl_Layer doesn't work when we do * this. So we use BRW_SURFACE_2D, since for rendering purposes this is * equivalent. */ surftype = BRW_SURFACE_2D; depth *= 6; break; So I guess we simply forgot to port this workaround to Vulkan. v2: tweak the conditions so the special case is cube texture sampling rather than anything else (Jason) Fixes: dEQP-VK.geometry.layered.cube* Reviewed-by: Jason Ekstrand <[email protected]>
* isl: fix VA64 support for double and dvecN vertex attributesSamuel Iglesias Gonsálvez2017-01-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | We use *64*_PASSTHRU formats to upload vertex attributes of 64 bits to avoid conversions. From the BDW PRM, Volume 2d, page 586 (VERTEX_ELEMENT_STATE): "When SourceElementFormat is set to one of the *64*_PASSTHRU formats, 64-bit components are stored in the URB without any conversion. In this case, vertex elements must be written as 128 or 256 bits, with VFCOMP_STORE_0 being used to pad the output as required. E.g., if R64_PASSTHRU is used to copy a 64-bit Red component into the URB, Component 1 must be specified as VFCOMP_STORE_0 (with Components 2,3 set to VFCOMP_NOSTORE) in order to output a 128-bit vertex element, or Components 1-3 must be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex element. Likewise, use of R64G64B64_PASSTHRU requires Component 3 to be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex element." v2,v3 (Jason): - Don't delete unused formats. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* isl: Mark A4B4G4R4_UNORM as supported on gen8Jason Ekstrand2017-01-061-1/+4
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Cc: "13.0" <[email protected]>
* isl: Make isl_finishme only warn once per call-siteEmil Velikov2016-11-281-1/+7
| | | | Signed-off-by: Emil Velikov <[email protected]>
* intel/isl: Allow non-2D CCS surfacesJason Ekstrand2016-11-171-2/+2
| | | | | | | | | The CCS calculations in ISL are already correct for 1-D and 3-D CCS surfaces since they have exactly the same layout as 2-D array surfaces (at least on Sky Lake). The only problem was that we weren't passing in the right dimensionality and we weren't passing in the depth. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Rework the asserts and fails in isl_surf_get_ccsJason Ekstrand2016-11-171-2/+7
| | | | | | | There are some invariants such as number of samples on which we should assert. However, most other things should silently return false since they're much easier for isl_surf_get_ccs to check than the caller. We also update the checking to be a bit more complete.
* intel/isl: Add some basic info about RENDER_SURFACE_STATE to isl_deviceJason Ekstrand2016-11-162-0/+30
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* isl: Fix height calculation in isl_msaa_interleaved_scale_px_to_saJordan Justen2016-11-151-1/+1
| | | | | | | | | | | | No known fixed tests, but it looks like a typo from: commit 8ac99eabb6570f0f3c5f7d7da1332a99ce636362 intel/isl: Add a helper for getting the size of an interleaved pixel Cc: "13.0" <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* isl: Only allow Y-tiling for ASTC texturesNanley Chery2016-11-031-0/+6
| | | | | Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* isl/format: Correct ASTC entries of format info tableNanley Chery2016-10-241-28/+42
| | | | | | | | | With the isl_format_supports* helpers, we can now conveniently report support for this format on Cherry View. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92925 Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* isl: use ifndef header guardsEmil Velikov2016-10-147-7/+28
| | | | | Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* isl: make locally used functions staticEmil Velikov2016-10-142-12/+2
| | | | | Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* isl: trivial include-what-you-want cleanupsEmil Velikov2016-10-145-5/+5
| | | | | | | Noticed while skimming through the files. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* isl/gen7: remove unneeded ISL_DEV_GEN checkEmil Velikov2016-10-141-3/+3
| | | | | | | | | | | | The function gen7_format_needs_valign2 has two callers - the gen7 only gen7_choose_valign_el() and isl_gen6_filter_tiling(). The latter of which already guarding the invocation appropriately. To be extra cautious add a couple of asserts alongside the removal of the runtime check. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* isl: prefix non-static API with isl_Emil Velikov2016-10-1411-116/+116
| | | | | | | | The rest of ISL already follows this approach. Be consistent and resolve the final references. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* isl/gen6: correctly check msaa layout samples countEmil Velikov2016-10-141-1/+1
| | | | | | | | | | | Samples == 1 is a valid value, so returning false is plain wrong. Seeming copy/paste typo introduced since day 1. Fixes: afdadec77f5 ("isl: Implement isl_surf_init() for gen4-gen9") Cc: [email protected] Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* isl: Correct a comment in the isl_format enumNanley Chery2016-10-071-1/+1
| | | | | | | | HiZ is not a color surface, but an auxiliary depth surface. Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/isl: Add an assert to check zero width/height surfaceAnuj Phogat2016-10-041-0/+3
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/isl: Allow non-2D HiZ surfacesJason Ekstrand2016-10-031-2/+2
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/isl: Add a detailed comment about multisampling with HiZJason Ekstrand2016-10-031-2/+58
| | | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/isl: Remove tiling checks from choose_msaa_layoutJason Ekstrand2016-10-032-14/+7
| | | | | | | | | | | We already do those checks in filter_tiling. There's no good reason to repeat them in choose_msaa_layout. If anything they should have been asserts and not "return false" checks. Also, this check was causing us to outright reject multisampled HiZ surfaces which wasn't intended. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/isl: Handle HiZ and CCS tiling more directlyJason Ekstrand2016-10-032-16/+16
| | | | | | | | | | | | The HiZ and CCS tiling formats are always used for HiZ and CCS surfaces respectively. There's no reason why we should go through filter_tiling and it's much easier to always get HiZ and CCS right if we just handle them directly. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/isl: Allow multisampling with ISL_FORMAT_HiZJason Ekstrand2016-10-032-3/+12
| | | | | | | | | | | | | HiZ buffers can be multisampled and, on Broadwell and earlier, simply using interleaved multisampling with a compression block size of 8x4 samples yields the correct HiZ surface size calculations. Unfortunately, choose_msaa_layout was rejecting multisampled HiZ buffers because of format checks. Now that we have a simple helper for determining if a format supports multisampling, that's an easy enough issue to fix. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/isl: Allow creation of 1-D compressed texturesJason Ekstrand2016-10-032-3/+11
| | | | | | | | | | | Compressed 1-D textures are not well-defined thing in either GL or Vulkan. However, auxiliary surfaces are treated as compressed textures in ISL and we can do HiZ and CCS with 1-D so we need to be able to create them. In order to prevent actually using them (the docs say no), we assert in the state setup code. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/isl: Fix up asserts in calc_phys_level0_extent_saJason Ekstrand2016-10-031-2/+4
| | | | | | | | | | | | | The assertion that a format is uncompressed in the multisample layouts isn't quite right. What we really want to assert is that the format supports multisampling which is a bit more complicated query. We also want to assert that it has a block size of 1x1 since we do nothing with the block size in the phys_level0_sa assignment. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/isl: Add a format_supports_multisampling helperJason Ekstrand2016-10-035-36/+33
| | | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/i965: make gen_device_info mutableLionel Landwerlin2016-09-231-6/+12
| | | | | | | | | | | | Make gen_device_info a mutable structure so we can update the fields that can be refined by querying the kernel (like subslices and EU numbers). This patch does not make any functional change, it just makes gen_get_device_info() fill a structure rather than returning a const pointer. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* isl: Finish tiling filtering for Gen6.Kenneth Graunke2016-09-153-5/+15
| | | | | | | | | | | | | Gen6 only has one additional restriction over Gen7+, so we just add it to the existing gen7 function (which actually covers later gens too). This should stop FINISHME spew when running GL on Sandybridge. v2: Fix bytes per block vs. bits per block confusion (Jason) and rename function to gen6_filter_tiling (Jason and Chad). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* Revert "intel/isl: Ignore base_array_layer and array_len for 3D storage..."Jason Ekstrand2016-09-131-6/+2
| | | | | | | | | This reverts commit 3943888c94beca69e575b8d3d1ec7a6cbf474ee4. It turns out that commit was pretty-much bogus since it breaks binding a 3-D texture as a 2-D storage image. The correct fix for the Vulkan CTS tests needs to be in the Vulkan driver itself rather than ISL. Signed-off-by: Jason Ekstrand <[email protected]>
* intel/isl: Divide QPitch by 2 for 3-D stencil textures on SKL+Jason Ekstrand2016-09-131-1/+14
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* isl/state: Don't set QPitch for GEN4_3D surfacesJason Ekstrand2016-09-131-1/+16
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* intel/isl: Ignore base_array_layer and array_len for 3D storage surfacesJason Ekstrand2016-09-131-2/+6
| | | | | | | | | | | | | | The time we want to restrict the Z range of a 3-D surface is when rendering to it. For storage surfaces, we always want he full range. However, we still need to set MinimumArrayElement and RenderTargetViewExtent to sensible values so we'll just set them to the reasonable defaults we used before we started respecting the base_array_layer and array_len. This fixes a bunch of Vulkan CTS regressions caused by 48f195d7c6483ed. Signed-off-by: Jason Ekstrand <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97790 Reviewed-by: Chad Versace <[email protected]>
* intel/isl: Add support for RGB formats in X and Y-tiled memoryJason Ekstrand2016-09-122-14/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Normally, using a non-linear tiling format helps improve cache locality by ensuring that neighboring pixels are usually close-by in memory. For RGB formats, this still sort-of holds, but it can also lead to rather terrible memory access patterns where a single RGB pixel value crosses a tile boundary and gets split into two pieces in different 4K pages. It also makes for some rather awkward calculations because your tile size is no longer an even multiple of surface element size. For these reasons, we chose to simply never create tiled RGB images in the Vulkan driver. The GL driver, however, is not so kind so we need to support it somehow. I briefly toyed with a couple of different schemes but this is the best one I could come up with. The fundamental problem is that a tile no longer contains an integer number of surface elements. I briefly considered a couple other options but found them wanting: 1) Using floats for the logical tile size. This leads to potential rounding error problems. 2) When presented with a RGB format, just make the tile 3-times as wide. This isn't so nice because now our tiles are no longer power-of-two size. Also, it can force the row_pitch to be larger than needed which, while not strictly a problem for ISL, causes incompatibility problems with the way the GL driver chooses surface pitches. The chosen method requires that you pay attention and not just assume that your tile_info is in the units you think it is. However, it's nice because it provides a nice "these are the units" declaration in isl_tile_info itself. Previously, the tile_info wasn't usable as a stand-alone structure because you had to also know the format. It also forces figuring out how to deal with inconsistencies between tiling and format back to the caller which is good because the two different consumers of isl_tile_info really want to deal with it differently: Computation of the surface size wants the fewest number of horizontal tiles possible while get_intratile_offset is far more concerned with things aligning nicely. Signed-off-by: Jason Ekstrand <[email protected]> Acked-by: Chad Versace <[email protected]>
* intel/isl: Allow valign2 for texture-only Y-tiled surfaces on gen7Jason Ekstrand2016-09-121-1/+2
| | | | | | | | | | The restriction that Y-tiled surfaces must have valign == 4 only aplies to render targets but we were applying it universally. This causes problems if ISL_FORMAT_R32G32B32_FLOAT is used because it requires valign == 2; this should be okay because you can't render to that format. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* intel/isl: Add a helper for getting the size of an interleaved pixelJason Ekstrand2016-09-122-5/+20
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
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