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path: root/src/intel/isl/isl.c
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* intel/isl: Allow stencil buffer to support compression on Gen12+Sagar Ghuge2019-10-291-2/+3
* intel/isl: Support lossless compression with multisamplesSagar Ghuge2019-10-281-5/+1
* intel/isl: Don't reconfigure aux surfaces for MCSSagar Ghuge2019-10-281-0/+3
* isl: Add isl_surf_supports_hiz_ccs_wt()Nanley Chery2019-10-281-0/+10
* intel: Support HIZ_CCS in isl_surf_get_ccs_surfNanley Chery2019-10-281-5/+34
* isl: Reduce assertions during aux surf creationNanley Chery2019-10-281-5/+15
* intel: Update alignment restrictions for HiZ surfaces.Jordan Justen2019-10-281-1/+7
* isl: Redefine the CCS layout for Gen12Nanley Chery2019-10-281-15/+115
* isl: Add and use isl_tiling_flag_to_enum()Nanley Chery2019-10-281-2/+2
* isl: Round up some pitches to 512B for Gen12's CCSNanley Chery2019-10-281-6/+14
* isl/gen12: 64k surface alignmentJordan Justen2019-10-281-0/+4
* intel/isl: Add gen12 depth/stencil surface alignmentsJordan Justen2019-10-171-1/+5
* intel/isl: Build gen12 using gen11 code pathsJordan Justen2019-08-281-0/+3
* intel: drop incorrect MAYBE_UNUSEDEric Engestrom2019-07-311-1/+1
* isl: Don't align phys_level0_sa by block dimensionNanley Chery2019-06-271-23/+15
* isl: tag unreachable path as suchEric Engestrom2019-06-201-0/+2
* isl: Add restrictions to isl_surf_get_hiz_surf()Nanley Chery2019-05-141-0/+25
* isl: Add restriction and comments to isl_surf_get_ccs_surf()Nanley Chery2019-05-141-1/+17
* isl: Modify restrictions in isl_surf_get_mcs_surf()Nanley Chery2019-05-141-5/+19
* intel/isl: Resize clear color buffer to full cachelineRafael Antognolli2019-04-241-1/+2
* isl: the display engine requires 64B alignment for linear surfacesSamuel Iglesias Gonsálvez2019-02-221-0/+8
* isl: remove the cache line size alignment requirementSamuel Iglesias Gonsálvez2019-02-201-14/+0
* isl: assert that Gen8+ don't have bit6_swizzlingCaio Marcelo de Oliveira Filho2019-02-041-0/+3
* intel/isl: move tiled_memcpy static libs from i965 to islTapani Pälli2019-01-101-0/+46
* intel/isl: Add a unit suffixes to some struct fields and variablesJason Ekstrand2018-09-261-54/+54
* i965: isl: Move the MCS gen7+ assertion into ISLNanley Chery2018-05-181-0/+2
* intel/isl: Add a helper for inverting swizzlesJason Ekstrand2018-05-091-0/+30
* intel/isl: Add a helper for composing swizzlesJason Ekstrand2018-05-091-0/+35
* intel/isl: Add an isl_swizzle_supports_rendering helperJason Ekstrand2018-05-091-0/+53
* intel: Use Clear Color struct size.Rafael Antognolli2018-04-051-0/+4
* intel/isl: Add an isl_color_value_is_zero helperJason Ekstrand2018-02-201-0/+20
* intel/isl/icl: Build and use gen11 surface state emit functionsAnuj Phogat2018-02-151-0/+3
* intel/isl/icl: Add the maximum surface size limitAnuj Phogat2018-02-151-1/+5
* isl: Add a null surface fill function.Kenneth Graunke2017-08-191-0/+7
* intel/isl: Replace switch statements of doom with a macroJason Ekstrand2017-08-171-96/+39
* isl: Validate row pitch of stencil surfaces.Kenneth Graunke2017-08-101-2/+7
* intel/isl: Don't align the height of the last array sliceJason Ekstrand2017-08-071-1/+2
* intel/isl: Stop padding surfacesJason Ekstrand2017-08-071-117/+2
* intel/isl: Add a helper to get a subimage surfaceJason Ekstrand2017-07-221-0/+41
* intel/isl: Add a helper for determining if a color is 0/1Jason Ekstrand2017-07-221-0/+27
* intel/isl: Add surface state clear value informationNanley Chery2017-07-221-0/+9
* intel/isl: Tighten up restrictions for CCS on gen7Jason Ekstrand2017-07-221-7/+23
* intel/isl: Allow 1D surfaces with compressed formatsTopi Pohjolainen2017-07-221-1/+1
* intel/isl: Align non-tiled horizontally by cache lineTopi Pohjolainen2017-07-221-1/+15
* intel/isl/gen4: Represent cube maps with 3D layoutTopi Pohjolainen2017-07-201-6/+35
* intel/isl: Add a row_pitch parameter to surf_get_ccs_surfJason Ekstrand2017-07-171-1/+3
* isl: use 64bit arithmetic to compute sizeLionel Landwerlin2017-07-131-2/+2
* Revert "intel/isl: Only create a CCS buffer if the image supports rendering"Nanley Chery2017-07-071-1/+1
* intel/isl: Only create a CCS buffer if the image supports renderingNanley Chery2017-06-261-1/+1
* intel/isl: Limit CCS to one level and layer on gen7Nanley Chery2017-06-261-2/+7
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