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* intel/isl: move tiled_memcpy static libs from i965 to islTapani Pälli2019-01-101-0/+46
| | | | | | | | | | | | | | Patch moves intel_tiled_memcpy[_sse41] libraries to isl, renames some functions and types and makes the required build system changes for meson, automake and Android. No functional changes are introduced. v2: code cleanups, move isl_get_memcpy_type to i965 (Jason) v3: move isl_mem_copy_fn to priv header, cleanups (Jason, Dylan) Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Dylan Baker <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* intel/isl: Add a unit suffixes to some struct fields and variablesJason Ekstrand2018-09-261-54/+54
| | | | | | | | | | | | | I was about to make the claim to someone that every field in isl_surf is either an enum or has explicit units. Then I looked at isl_surf and discovered this claim was wrong. We should fix that. This commit does a few refactors: * Add _B suffixes to some struct fields * Add _B to some variables and parameters * Rename row_pitch_tiles -> row_pitch_tl Reviewed-by: Nanley Chery <[email protected]>
* i965: isl: Move the MCS gen7+ assertion into ISLNanley Chery2018-05-181-0/+2
| | | | | | | This is useful for every user of ISL. Drop the comment along the way to match similar functions in ISL. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add a helper for inverting swizzlesJason Ekstrand2018-05-091-0/+30
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add a helper for composing swizzlesJason Ekstrand2018-05-091-0/+35
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/isl: Add an isl_swizzle_supports_rendering helperJason Ekstrand2018-05-091-0/+53
| | | | | | | This helper encodes more details, specifically about Haswell, than the previous asserts in isl_surface_state.c. Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Use Clear Color struct size.Rafael Antognolli2018-04-051-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The size of the clear color struct (expected by the hardware) is 8 dwords (isl_dev.ss.clear_value_state_size here). But we still need to track the size of the clear color, used when memcopying it to/from the state buffer. For that we keep isl_dev.ss.clear_value_size. v4: - Add struct to gen11 too (Jason, Jordan) - Add field for Converted Clear Color to gen11 (Jason) - Add clear_color_state_offset to differentiate from clear_value_offset. - Fix all the places where clear_value_size was used. v5 (Jason): - Split genxml changes to another commit. - Remove unnecessary gen checks. - Bring back missing offset increment to init_fast_clear_color(). v6 (Jason): - On init_fast_clear_color, change: addr.offset += 4 => sdi.Address.offset += i * 4 - Use GEN_GEN instead of GEN_VERSIONx10. [[email protected]: isl_device_init changes] Signed-off-by: Rafael Antognolli <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/isl: Add an isl_color_value_is_zero helperJason Ekstrand2018-02-201-0/+20
| | | | | Cc: [email protected] Reviewed-by: Nanley Chery <[email protected]>
* intel/isl/icl: Build and use gen11 surface state emit functionsAnuj Phogat2018-02-151-0/+3
| | | | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* intel/isl/icl: Add the maximum surface size limitAnuj Phogat2018-02-151-1/+5
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* isl: Add a null surface fill function.Kenneth Graunke2017-08-191-0/+7
| | | | | | | | | | ISL already offers functions to fill out most kinds of SURFACE_STATE, so why not handle null surfaces too? Null surfaces are simple, so we can just take the dimensions, rather than an entirte fill structure. Reviewed-by: Jason Ekstrand <[email protected]>
* intel/isl: Replace switch statements of doom with a macroJason Ekstrand2017-08-171-96/+39
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* isl: Validate row pitch of stencil surfaces.Kenneth Graunke2017-08-101-2/+7
| | | | | | | | | | | | Also, silence an obnoxious finishme that started occurring for all GL applications which use stencil after the i965 ISL conversion. v2: Check against 3DSTATE_STENCIL_BUFFER's pitch bits when using separate stencil, and 3DSTATE_DEPTH_BUFFER's bits when using combined depth-stencil. Cc: "17.2" <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/isl: Don't align the height of the last array sliceJason Ekstrand2017-08-071-1/+2
| | | | | | | | | | | | | We were calculating the total height of 2D surfaces by multiplying the row pitch by the number of slices. This means that we actually request slightly more space than actually needed since the padding on the last slice is unnecessary. For tiled surfaces this is not likely to make a difference. For linear surfaces, on the other hand, this means we may require additional memory. In particular, this makes the i965 driver reject EGL imports of buffers which do not have this extra padding. Reviewed-by: Jordan Justen <[email protected]> Cc: "17.2" <[email protected]>
* intel/isl: Stop padding surfacesJason Ekstrand2017-08-071-117/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The docs contain a bunch of commentary about the need to pad various surfaces out to multiples of something or other. However, all of those requirements are about avoiding GTT errors due to missing pages when the data port or sampler accesses slightly out-of-bounds. However, because the kernel already fills all the empty space in our GTT with the scratch page, we never have to worry about faulting due to OOB reads. There are two caveats to this: 1) There is some potential for issues with caches here if extra data ends up in a cache we don't expect due to OOB reads. However, because we always trash the entire cache whenever we need to move anything between cache domains, this shouldn't be an issue. 2) There is a potential issue if a surface gets placed at the very top of the GTT by the kernel. In this case, the hardware could potentially end up trying to read past the top of the GTT. If it nicely wraps around at the 48-bit (or 32-bit) boundary, then this shouldn't be an issue thanks to the scratch page. If it doesn't, then we need to come up with something to handle it. Up until some of the GL move to ISL, having the padding code in there just caused us to harmlessly use a bit more memory in Vulkan. However, now that we're using ISL sizes to validate external dma-buf images, these padding requirements are causing us to reject otherwise valid images due to the size of the BO being too small. Acked-by: Kenneth Graunke <[email protected]> Tested-by: Tapani Pälli <[email protected]> Tested-by: Tomasz Figa <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Cc: "17.2" <[email protected]>
* intel/isl: Add a helper to get a subimage surfaceJason Ekstrand2017-07-221-0/+41
| | | | | | | We already have a helper for doing this in BLORP, this just moves the logic into ISL where we can share it with other components. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/isl: Add a helper for determining if a color is 0/1Jason Ekstrand2017-07-221-0/+27
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add surface state clear value informationNanley Chery2017-07-221-0/+9
| | | | | | | | This will be used to load and store clear values from surface state objects. Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/isl: Tighten up restrictions for CCS on gen7Jason Ekstrand2017-07-221-7/+23
| | | | | | | | | | It may technically be possible to enable some sort of fast-clear support for at least the base slice of a 2D array texture on gen7. However, it's not documented to work, we've never tried to do it in GL, and we have no idea what the hardware does if you turn on CCS_D with arrayed rendering. Let's just play it safe and disallow it for now. If someone really cares that much about gen7 performance, they can come along and try to get it working later.
* intel/isl: Allow 1D surfaces with compressed formatsTopi Pohjolainen2017-07-221-1/+1
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* intel/isl: Align non-tiled horizontally by cache lineTopi Pohjolainen2017-07-221-1/+15
| | | | | | | in order to support blit engine. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* intel/isl/gen4: Represent cube maps with 3D layoutTopi Pohjolainen2017-07-201-6/+35
| | | | | | | v2 (Jason): Check for !ISL_SURF_DIM_3D instead of CUBE_BIT. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add a row_pitch parameter to surf_get_ccs_surfJason Ekstrand2017-07-171-1/+3
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* isl: use 64bit arithmetic to compute sizeLionel Landwerlin2017-07-131-2/+2
| | | | | | | | | If we allow the size to be more than 2^32, then we should compute it in 64bit arithmetic otherwise we might run into overflow issues. CID: 1412892, 1412891 Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* Revert "intel/isl: Only create a CCS buffer if the image supports rendering"Nanley Chery2017-07-071-1/+1
| | | | | | | | | This reverts commit 8aaa13467dc289d35dc7900ab9fab9a7689c4178, which was based on an incorrect assumption. Unlike the restriction placed on image views in the Vulkan API, OpenGL allows you to render to texture views whose formats differ from the originals. Bugzilla: https://bugzilla.freedesktop.org/show_bug.cgi?id=101677
* intel/isl: Only create a CCS buffer if the image supports renderingNanley Chery2017-06-261-1/+1
| | | | | | | | v2: Omit the commit message. Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/isl: Limit CCS to one level and layer on gen7Nanley Chery2017-06-261-2/+7
| | | | | | | | | | v2 (Jason Ekstrand): - Remove Vulkan-specific terminology from the commit title. - Replace '== 7' with '<= 7' to hint that this is a new feature on BDW+. Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> (v1) Reviewed-by: Jason Ekstrand <[email protected]>
* intel/isl/gen6: Allow arrayed stencilTopi Pohjolainen2017-06-171-1/+0
| | | | | | | | Nothing prevents arrayed stencil surfaces even though hardware doesn't support mipmapping. Reviewed-by: Nanley Chery <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add the maximum surface size limitAnuj Phogat2017-06-161-0/+22
| | | | | | | | V2: Use 2^31 bytes (2GB) surface size limit on pre-gen9 and 2^38 bytes for gen9+. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/isl: Use uint64_t to store total surface sizeAnuj Phogat2017-06-161-1/+2
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* i965/cnl: Handle gen10 in switch cases across the driverAnuj Phogat2017-06-091-0/+9
| | | | | | | | | V2: Start using gen10 functions isl_gen10*(), gen10_blorp_exec() gen10_init_atoms() (Jason) Remove Vulkan changes. Do them later in a separate patch. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/isl: Add a helper for getting the byte/tile offset of a subimageJason Ekstrand2017-06-011-0/+39
| | | | | | | | | Frequently, get_image_offset_sa is combined with get_intratile_offset_sa so it makes sense to have a single helper to do both. If the caller doesn't want the intratile offsets, it can simply pass NULL and ISL will assert that they are 0. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Make get_intratile_offset_el take the element size in bitsJason Ekstrand2017-06-011-4/+3
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add a new layout for HiZ and stencil on Sandy BridgeJason Ekstrand2017-06-011-5/+157
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Generate phys_total_el from isl_calc_phys_extentJason Ekstrand2017-06-011-68/+97
| | | | | | | | | | The only surface layout for which slice0 makes any sense is GEN4_2D. Move all of the slice0 stuff into isl_calc_phys_total_extent_el_gen4_2d and make the others trivially return the total size in surface elements. As a side-effect, array_pitch_el_rows is now returned from these helpers as well. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Refactor to use a phys_total_el extent.Jason Ekstrand2017-06-011-19/+19
| | | | | | | We've already implicitly been using a physical total size in surface elements. This just centralizes things a bit. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Refactor isl_calc_array_pitch_el_rowsJason Ekstrand2017-06-011-47/+46
| | | | | | | | | | | Over 90% of the function only applies to ISL_DIM_LAYOUT_GEN4_2D anyway so we can just handle the other two as special cases at the top. The two "generic" cases below the switch only apply on gen9 and above and only to 3D or CCS surfaces. This implies that they only apply to surfaces with ISL_DIM_LAYOUT_GEN4_2D. Making them look generic is a lie. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Move isl_calc_array_pitch_el_rows higher upJason Ekstrand2017-06-011-117/+117
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Remove the device parameter from isl_tiling_get_infoJason Ekstrand2017-06-011-20/+9
| | | | | | | | | We were only using it for validating that we don't use Ys/Yf on gen8 and earlier. Removing it from isl_tiling_get_info lets us remove it from a bunch of other things that had no business needing a hardware generation. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add gen4_filter_tilingJason Ekstrand2017-05-261-2/+1
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add support for gen4 cube maps to get_image_offset_saJason Ekstrand2017-05-261-5/+18
| | | | | | | Gen4 cube maps are a 2-D surface with ISL_DIM_LAYOUT_GEN4_3D which is a bit weird but accurate none the less. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Don't request space for stencil/hiz packets unless neededJason Ekstrand2017-05-261-7/+6
| | | | | | | On Iron Lake, the packets exist but we never emit them so there's no need for us to ask the driver to make batch space for them. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add support for emitting depth/stencil/hizJason Ekstrand2017-04-101-0/+93
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Use genx_bits.h instead of a hand-rolled tableJason Ekstrand2017-04-071-18/+13
| | | | | | | | This gets rid of one piece of ugliness with the way ISL handles surface emitting surface states. I've never liked that hand-rolled table but it was the best we had at the time. Reviewed-by: Topi Pohjolainen <[email protected]>
* isl: Drop unused isl_surf_init_info::min_pitchChad Versace2017-03-281-10/+3
| | | | | | Reviewed-by: Nanley Chery <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* isl: Let isl_surf_init's caller set the exact row pitch (v2)Chad Versace2017-03-281-1/+13
| | | | | | | | | The caller does so by setting the new field isl_surf_init_info::row_pitch. v2: Validate the requested row_pitch. Reviewed-by: Jason Ekstrand <[email protected]> (v2)
* isl: Validate the calculated row pitch (v45)Chad Versace2017-03-281-6/+64
| | | | | | | | | | | | | | | | | | | | | | | | Validate that isl_surf::row_pitch fits in the below bitfields, if applicable based on isl_surf::usage. RENDER_SURFACE_STATE::SurfacePitch RENDER_SURFACE_STATE::AuxiliarySurfacePitch 3DSTATE_DEPTH_BUFFER::SurfacePitch 3DSTATE_HIER_DEPTH_BUFFER::SurfacePitch v2: -Add a Makefile dependency on generated header genX_bits.h. v3: - Test ISL_SURF_USAGE_STORAGE_BIT too. [for jekstrand] - Drop explicity dependency on generated header. [for emil] v4: - Rebase for new gen_bits_header.py script. - Replace gen_10x with gen_device_info*. v5: - Drop FINISHME for validation of GEN9 1D row pitch. [for jekstrand] - Reformat bit tests. [for jekstrand] Reviewed-by: Jason Ekstrand <[email protected]> (v4)
* isl: Refactor row pitch calculation (v2)Chad Versace2017-03-211-33/+89
| | | | | | | | | | | | | | | | | The calculations of row_pitch, the row pitch's alignment, surface size, and base_alignment were mixed together. This patch moves the calculation of row_pitch and its alignment to occur before the calculation of surface_size and base_alignment. This simplifies a follow-on patch that adds a new member, 'row_pitch', to struct isl_surf_init_info. v2: - Also extract the row pitch alignment. - More helper functions that will later help validate the row pitch. Reviewed-by: Nanley Chery <[email protected]> (v2) Reviewed-by: Jason Ekstrand <[email protected]> (v2)
* isl: Drop misplaced comment about paddingChad Versace2017-03-211-46/+0
| | | | | | | | | | | | | isl has a giant comment that explains the hardware's padding requirements. (Hint: Cache lines and page faults). But the comment is in the wrong place, in isl_calc_linear_row_pitch(), which is unrelated to padding. The important parts of that comment were copied to isl_apply_surface_padding() long ago. So drop the misplaced comment. Reviewed-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel: Correct the BDW surface state sizeNanley Chery2017-03-201-1/+1
| | | | | | | | | | | The PRMs state that this packet is 16 DWORDS long. Ensure that the last three DWORDS are zeroed as required by the hardware when allocating a null surface state. Cc: <[email protected]> Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
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