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* intel/batch_decoder: decoding of 3DSTATE_CONSTANT_BODY.Sergii Romantsov2018-07-161-24/+14
| | | | | | | | | | | | | | SNB doesn't have a definition of 3DSTATE_CONSTANT_BODY, thats why we got segmentation fault when used INTEL_DEBUG=bat. Fixed by adding of 3DSTATE_CONSTANT_BODY into 3DSTATE_CONSTANT of VS, GS and PS structures. v2: added definition of 3DSTATE_CONSTANT_BODY to the gen6.xml Fixes: 169d8e011ae (intel: Fix 3DSTATE_CONSTANT buffer decoding.) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107190 Signed-off-by: Sergii Romantsov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: Add bitmasks for CS_DEBUG_MODE2/INSTPM.Rafael Antognolli2018-06-187-0/+32
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Assert that genxml field start and ends are sane.Kenneth Graunke2018-05-071-0/+7
| | | | | | | | | Chris recently fixed a bunch of genxml end < start bugs, as well as booleans that are wider than a bit. These are way too easy to write, so asserting that the fields are sane is a good plan. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* intel/genxml: Fix some more fake booleans in genxml.Kenneth Graunke2018-05-075-11/+11
| | | | | | | | | None of these are actually booleans. Tile Parameter is a tiling mode enum. Display pipes take plane numbers. Predicate Enable has some operations (and the default value of 6 was particular bogus). Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/genxml: Make assert in gen_pack_header print a message.Kenneth Graunke2018-05-071-1/+1
| | | | | | | | | | Python's assert can take both a condition and a string, which will cause it to print the string if the assertion trips. (You can't use parens as that creates a tuple.) Doing "condition and string" works in C, but doesn't have the desired effect in Python. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/genxml: Fix a few invalid field widthsChris Wilson2018-05-076-28/+28
| | | | | | | | | | A couple of typos found by inspecting field.end - field.start, revealed a few wide integers declared as bool and some that ended before they started. Cc: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: recognize 0x, 0o and 0b when setting default valueCaio Marcelo de Oliveira Filho2018-05-041-1/+2
| | | | | | | | | | | | | Remove the need of converting values that are documented in hexadecimal. This patch would allow writing <field name="3D Command Sub Opcode" ... default="0x1B"/> instead of <field name="3D Command Sub Opcode" ... default="27"/> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Add Clear Color struct to gen10+.Rafael Antognolli2018-04-052-0/+18
| | | | | | | v5: Split genxml changes into its own commit (Jason). Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/genxml: Use a single field for clear color address on gen10.Rafael Antognolli2018-04-052-8/+6
| | | | | | | | | | | | | | | | | | | | genxml does not support having two address fields with different names but same position in the state struct. Both "Clear Color Address" and "Clear Depth Address Low" mean the same thing, only for different surface types. To workaround this genxml limitation, rename "Clear Color Address" to "Clear Value Address" and use it for both color and depth. Do the same for the high bits. TODO: add support for multiple addresses at the same position in the xml. v2: Combine high and low order bits into a single address field. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* genxml: Preserve fields that share dword space with addresses.Rafael Antognolli2018-04-051-2/+6
| | | | | | | | | | | | | | | | | Some instructions contain fields that are either an address or a value of some type based on the content of other fields, such as clear color values vs address. That works fine if these fields are in the less significant dword, the lower 32 bits of the address, because they get OR'ed with the address. But if they are in the higher 32 bits, they get discarded. On Gen10 we have fields that share space with the higher 16 bits of the address too. This commit makes sure those fields don't get discarded. v5: Remove spurious whitespace (Jason). Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel: genxml: decode variable length MI_LRILionel Landwerlin2018-04-0310-0/+40
| | | | | | | | | | | | | | | MI_LOAD_REGISTER_IMM can load multiple (register, value) tuples in one command. In our drivers we only use one tuple at a time, but the kernel might load more than one at a time. Instead of making all the tuple part of a group, we leave out the first tuple (the one we use in the generated packing structures). This is particularly useful for looking at error stats generated by the kernel. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* intel: genxml: add preemption control instructionsLionel Landwerlin2018-04-034-0/+26
| | | | | | | Helpful to debug kernel workaround batchbuffers. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* intel/genxml: Add SAMPLER_INSTDONE register.Rafael Antognolli2018-03-266-0/+139
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Add ROW_INSTDONE register.Rafael Antognolli2018-03-266-0/+114
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Add SC_INSTDONE register.Rafael Antognolli2018-03-266-0/+140
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* intel: genxml: add INSTPM/CS_DEBUG_MODE2 registersLionel Landwerlin2018-03-207-0/+46
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Drop SURFACE_FORMAT enum from genxml.Kenneth Graunke2018-03-0510-2251/+17
| | | | | | | | | | | We want people to be using ISL_FORMAT_*, rather than the genxml format enumerations. This patch drops 10 separate copies, and drops a bunch of ugly casting. Reviewed-by: Jordan Justen <[email protected]> [[email protected]: Minor changes for rebase] Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* intel: Split gen_device_info out into libintel_devJordan Justen2018-03-051-1/+1
| | | | | | | | | | | | Split out the device info so isl doesn't depend on intel/common. Now it will depend on the new intel/dev device info lib. This will allow the decoder in intel/common to use isl, allowing us to apply Ken's patch that removes the genxml duplication of surface formats. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* genxml: Silence unused parameter warnings in generated pack codeIan Romanick2018-03-021-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | Reduces my build from 1960 warnings to 1808 warnings by silencing 152 instances of things like In file included from ../../SOURCE/master/src/intel/genxml/genX_pack.h:32:0, from ../../SOURCE/master/src/intel/isl/isl_emit_depth_stencil.c:36: src/intel/genxml/gen4_pack.h: In function ‘__gen_uint’: src/intel/genxml/gen4_pack.h:58:49: warning: unused parameter ‘end’ [-Wunused-parameter] __gen_uint(uint64_t v, uint32_t start, uint32_t end) ^~~ src/intel/genxml/gen4_pack.h: In function ‘__gen_offset’: src/intel/genxml/gen4_pack.h:94:35: warning: unused parameter ‘start’ [-Wunused-parameter] __gen_offset(uint64_t v, uint32_t start, uint32_t end) ^~~~~ src/intel/genxml/gen4_pack.h:94:51: warning: unused parameter ‘end’ [-Wunused-parameter] __gen_offset(uint64_t v, uint32_t start, uint32_t end) ^~~ src/intel/genxml/gen4_pack.h: In function ‘__gen_ufixed’: src/intel/genxml/gen4_pack.h:133:48: warning: unused parameter ‘end’ [-Wunused-parameter] __gen_ufixed(float v, uint32_t start, uint32_t end, uint32_t fract_bits) ^~~ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* intel/genxml/icl: Update genx_bits headerAnuj Phogat2018-02-151-0/+1
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml/icl: Generate packing headersAnuj Phogat2018-02-153-0/+6
| | | | | | | | | Move build system changes in to one patch (Ken, Emil) Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* intel/genxml/icl: Add gen11.xmlAnuj Phogat2018-02-151-0/+3765
| | | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* meson: don't use intermediate variables that are immediately discardedDylan Baker2018-01-111-2/+1
| | | | | | | | | | | | | | | | For things like: loop x = func() list += x end just do: loop list += func() end Acked-by: Eric Engestrom <[email protected]> Signed-off-by: Dylan Baker <[email protected]>
* genxml: Add missing INSTDONE_1 bits on Gen7.5+.Kenneth Graunke2018-01-094-0/+8
| | | | | | This will make aubinator_error_decode decode them properly. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel: Apply Geminilake "Barrier Mode" workaround.Kenneth Graunke2018-01-091-0/+8
| | | | | | | | | | | | | | | | | | | Apparently, Geminilake requires you to whack a chicken bit to select either compute or tessellation mode for barriers. The recommendation is to switch between them at PIPELINE_SELECT time. We may not need to do this all the time, but I don't know that it hurts either. PIPELINE_SELECT is already a pretty giant stall. This appears to fix hangs in tessellation control shaders with barriers on Geminilake. Note that this requires a corresponding kernel change, drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake. in order for the register write to actually happen. Without an updated kernel, this register write will be noop'd and the fix will not work. Reviewed-by: Rafael Antognolli <[email protected]>
* genxml: fix assert guardsEric Engestrom2017-11-231-5/+5
| | | | | | | This removes a few hundred warnings on debug builds with asserts off. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: Add helpers for determining field typeKristian H. Kristensen2017-11-211-6/+17
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* genxml: Fix PIPELINE_SELECT on G45/Ironlake.Kenneth Graunke2017-11-162-2/+2
| | | | | | | | | Original 965 sets bits 28:27 to 0, while G45 and later set it to 1. Note that the G45 docs are incorrect in this regard - see the DevCTG+ note in the Ironlake PRMs. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Add Cache Mode SubSlice Register to gen10.xmlAnuj Phogat2017-11-141-0/+12
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: Delete empty groupsJason Ekstrand2017-11-134-8/+0
| | | | | | | | | They serve no purpose other than to just fill empty space in the packet so each dword has something. Just disallowing empty groups is a bit easier on some of the tools. This does not change the generated packing headers in any way. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel: Make Cube Face Enable fields consistent across generations.Kenneth Graunke2017-10-036-6/+36
| | | | | | | | I decided to use the one-boolean-per-cube-face approach because it's clearer which bits correspond to which cube face. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* meson: Add build Intel "anv" vulkan driverDylan Baker2017-09-271-0/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows building and installing the Intel "anv" Vulkan driver using meson and ninja, the driver has been tested against the CTS and has seems to pass the same series of tests (they both segfault when the CTS tries to run wayland wsi tests). There are still a mess of TODO, XXX, and FIXME comments in here. Those are mostly for meson bugs I'm trying to fix, or for additional things to implement for other drivers/features. I have configured all intermediate libraries and optional tools to not build by default, meaning they will only be built if they're pulled in as a dependency of a target that will actually be installed) this allows us to avoid massive if chains, while ensuring that only the bits that need to be built are. v2: - enable anv, x11, and wayland by default - add configure option to disable valgrind v3: - fix typo in meson_options (Nicholas) v4: - Remove dead code (Eric) - Remove change to generator that was from v0 (Eric) - replace if chain with loop (Eric) - Fix typos (Eric) - define HAVE_DLOPEN for both libdl and builtin dl cases (Eric) v5: - rebase on util string buffer implementation Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]> (v4)
* intel/genxml: Convert a not-present-or-"1" dict to a set.Eric Anholt2017-09-261-2/+3
| | | | | | | I was implementing the same enum support in broadcom's gen_pack_header.py, and did this same simplification there. Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Make Border Color Pointer an address on Gen4-5, not an offset.Kenneth Graunke2017-09-023-3/+3
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* intel/genxml: Fix gen10 BLEND_STATE variable length packingScott D Phillips2017-08-151-2/+2
| | | | | | | | | | | | | | | | BLEND_STATE packing was modified to be variable-length in: 9670124e31 genxml: Make BLEND_STATE command support variable length array. The initial gen10.xml still had the old, fixed-length style definition for BLEND_STATE. So gen10_upload_blend_state would overwrite the packed BLEND_STATE_ENTRYs with its own fixed array of all-zero entries when packing BLEND_STATE. This caused BLEND_STATE upload to not work at all. Fixes: aa416f515a ("i965/genxml: Add gen10.xml") Reviewed-by: Rafael Antognolli <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* intel: genxml: make a couple of enums show up in aubinatorLionel Landwerlin2017-07-026-45/+47
| | | | | | | In particular Shader Channel Select & Texture Address Control Mode. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* genxml: Silence about a billion unused parameter warningsIan Romanick2017-06-281-2/+7
| | | | | | | | | | v2: Use textwrap.dedent to make the source line a lot shorter. Shortening (?) the line was requested by Jason. v3: Simplify the texwrap.dedent usage. Suggested by Dylan. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* genxml: fix gen5 sampler border color state.Rafael Antognolli2017-06-221-20/+20
| | | | | | | | Based on the current code, gen5 and gen6 have the same sampler border color state struct. So fix the gen5 one to match gen6. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Add Gen10 CACHE_MODE_1 definitionsAnuj Phogat2017-06-221-0/+18
| | | | | | | | | | Few of the fields in this register are changed as compared to gen9.xml. V2: Remove some fields which are not valid anymore. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: Rename StartInstanceLocation to StartingInstanceLocationAnuj Phogat2017-06-221-1/+1
| | | | | | | | This is required because we already have a macro defined with the name StartInstanceLocation. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: Rename IndirectStatePointer to BorderColorPointerAnuj Phogat2017-06-221-1/+1
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: Combine DataDWord{0, 1} fields in to ImmediateData fieldAnuj Phogat2017-06-221-2/+1
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: Add INSTDONE registers in gen10Anuj Phogat2017-06-221-0/+115
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: Add better support for MI_MATH in gen10Anuj Phogat2017-06-221-4/+65
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: Use the same naming convention for Floating Point Mode.Rafael Antognolli2017-06-211-2/+2
| | | | | | | | In newer gens, this field has a prefix and the non-IEEEE-745 mode is called "Alternate", instead of simply "Alt". Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: Normalize URB Data field in WM_STATE.Rafael Antognolli2017-06-213-3/+3
| | | | | | | | | | On gen6+, this is called "Dispatch GRF Start Register For Constant/Setup Data 0", while on gen5 and lower it's called only "Dispatch GRF Start Register For URB Data", but it's essentially the same thing (URB data), so rename it to match newer gens and simplify the C code that handles it. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: Rename field on WM_STATE to match gen6+.Rafael Antognolli2017-06-213-3/+3
| | | | | | | | "Pixel Shader Kill Pixel" -> "Pixel Shader Kills Pixel", which is how it's called on newer gens. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: Normalize fields on WM_STATE.Rafael Antognolli2017-06-212-4/+4
| | | | | | | | | On gen4, WM_STATE only has one Kernel Start Pointer and one GRF Register Count, but we can make the code that handles this on multiple gens simpler if we add an index 0 to it too. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: Add missing field to CLIP_STATE.Rafael Antognolli2017-06-212-0/+5
| | | | | | | | | | | Just because it's not set doesn't mean that it doesn't exist. And since the field is there on newer gens, having it on gen5 simplifies the code when porting gen5 and lower. Also add missing value to API Mode on CLIP_STATE on gen4. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: Fix type of UserClipFlags ClipTest Enable Bitmask.Rafael Antognolli2017-06-213-3/+3
| | | | | | | | This is a bitmask, so it can't be a boolean. Also rename it so it matches gen6+. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
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