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* meson: don't use intermediate variables that are immediately discardedDylan Baker2018-01-111-2/+1
| | | | | | | | | | | | | | | | For things like: loop x = func() list += x end just do: loop list += func() end Acked-by: Eric Engestrom <[email protected]> Signed-off-by: Dylan Baker <[email protected]>
* genxml: Add missing INSTDONE_1 bits on Gen7.5+.Kenneth Graunke2018-01-094-0/+8
| | | | | | This will make aubinator_error_decode decode them properly. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel: Apply Geminilake "Barrier Mode" workaround.Kenneth Graunke2018-01-091-0/+8
| | | | | | | | | | | | | | | | | | | Apparently, Geminilake requires you to whack a chicken bit to select either compute or tessellation mode for barriers. The recommendation is to switch between them at PIPELINE_SELECT time. We may not need to do this all the time, but I don't know that it hurts either. PIPELINE_SELECT is already a pretty giant stall. This appears to fix hangs in tessellation control shaders with barriers on Geminilake. Note that this requires a corresponding kernel change, drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake. in order for the register write to actually happen. Without an updated kernel, this register write will be noop'd and the fix will not work. Reviewed-by: Rafael Antognolli <[email protected]>
* genxml: fix assert guardsEric Engestrom2017-11-231-5/+5
| | | | | | | This removes a few hundred warnings on debug builds with asserts off. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: Add helpers for determining field typeKristian H. Kristensen2017-11-211-6/+17
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* genxml: Fix PIPELINE_SELECT on G45/Ironlake.Kenneth Graunke2017-11-162-2/+2
| | | | | | | | | Original 965 sets bits 28:27 to 0, while G45 and later set it to 1. Note that the G45 docs are incorrect in this regard - see the DevCTG+ note in the Ironlake PRMs. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Add Cache Mode SubSlice Register to gen10.xmlAnuj Phogat2017-11-141-0/+12
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: Delete empty groupsJason Ekstrand2017-11-134-8/+0
| | | | | | | | | They serve no purpose other than to just fill empty space in the packet so each dword has something. Just disallowing empty groups is a bit easier on some of the tools. This does not change the generated packing headers in any way. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel: Make Cube Face Enable fields consistent across generations.Kenneth Graunke2017-10-036-6/+36
| | | | | | | | I decided to use the one-boolean-per-cube-face approach because it's clearer which bits correspond to which cube face. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* meson: Add build Intel "anv" vulkan driverDylan Baker2017-09-271-0/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows building and installing the Intel "anv" Vulkan driver using meson and ninja, the driver has been tested against the CTS and has seems to pass the same series of tests (they both segfault when the CTS tries to run wayland wsi tests). There are still a mess of TODO, XXX, and FIXME comments in here. Those are mostly for meson bugs I'm trying to fix, or for additional things to implement for other drivers/features. I have configured all intermediate libraries and optional tools to not build by default, meaning they will only be built if they're pulled in as a dependency of a target that will actually be installed) this allows us to avoid massive if chains, while ensuring that only the bits that need to be built are. v2: - enable anv, x11, and wayland by default - add configure option to disable valgrind v3: - fix typo in meson_options (Nicholas) v4: - Remove dead code (Eric) - Remove change to generator that was from v0 (Eric) - replace if chain with loop (Eric) - Fix typos (Eric) - define HAVE_DLOPEN for both libdl and builtin dl cases (Eric) v5: - rebase on util string buffer implementation Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]> (v4)
* intel/genxml: Convert a not-present-or-"1" dict to a set.Eric Anholt2017-09-261-2/+3
| | | | | | | I was implementing the same enum support in broadcom's gen_pack_header.py, and did this same simplification there. Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Make Border Color Pointer an address on Gen4-5, not an offset.Kenneth Graunke2017-09-023-3/+3
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* intel/genxml: Fix gen10 BLEND_STATE variable length packingScott D Phillips2017-08-151-2/+2
| | | | | | | | | | | | | | | | BLEND_STATE packing was modified to be variable-length in: 9670124e31 genxml: Make BLEND_STATE command support variable length array. The initial gen10.xml still had the old, fixed-length style definition for BLEND_STATE. So gen10_upload_blend_state would overwrite the packed BLEND_STATE_ENTRYs with its own fixed array of all-zero entries when packing BLEND_STATE. This caused BLEND_STATE upload to not work at all. Fixes: aa416f515a ("i965/genxml: Add gen10.xml") Reviewed-by: Rafael Antognolli <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* intel: genxml: make a couple of enums show up in aubinatorLionel Landwerlin2017-07-026-45/+47
| | | | | | | In particular Shader Channel Select & Texture Address Control Mode. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* genxml: Silence about a billion unused parameter warningsIan Romanick2017-06-281-2/+7
| | | | | | | | | | v2: Use textwrap.dedent to make the source line a lot shorter. Shortening (?) the line was requested by Jason. v3: Simplify the texwrap.dedent usage. Suggested by Dylan. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* genxml: fix gen5 sampler border color state.Rafael Antognolli2017-06-221-20/+20
| | | | | | | | Based on the current code, gen5 and gen6 have the same sampler border color state struct. So fix the gen5 one to match gen6. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Add Gen10 CACHE_MODE_1 definitionsAnuj Phogat2017-06-221-0/+18
| | | | | | | | | | Few of the fields in this register are changed as compared to gen9.xml. V2: Remove some fields which are not valid anymore. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: Rename StartInstanceLocation to StartingInstanceLocationAnuj Phogat2017-06-221-1/+1
| | | | | | | | This is required because we already have a macro defined with the name StartInstanceLocation. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: Rename IndirectStatePointer to BorderColorPointerAnuj Phogat2017-06-221-1/+1
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: Combine DataDWord{0, 1} fields in to ImmediateData fieldAnuj Phogat2017-06-221-2/+1
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: Add INSTDONE registers in gen10Anuj Phogat2017-06-221-0/+115
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: Add better support for MI_MATH in gen10Anuj Phogat2017-06-221-4/+65
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: Use the same naming convention for Floating Point Mode.Rafael Antognolli2017-06-211-2/+2
| | | | | | | | In newer gens, this field has a prefix and the non-IEEEE-745 mode is called "Alternate", instead of simply "Alt". Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: Normalize URB Data field in WM_STATE.Rafael Antognolli2017-06-213-3/+3
| | | | | | | | | | On gen6+, this is called "Dispatch GRF Start Register For Constant/Setup Data 0", while on gen5 and lower it's called only "Dispatch GRF Start Register For URB Data", but it's essentially the same thing (URB data), so rename it to match newer gens and simplify the C code that handles it. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: Rename field on WM_STATE to match gen6+.Rafael Antognolli2017-06-213-3/+3
| | | | | | | | "Pixel Shader Kill Pixel" -> "Pixel Shader Kills Pixel", which is how it's called on newer gens. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: Normalize fields on WM_STATE.Rafael Antognolli2017-06-212-4/+4
| | | | | | | | | On gen4, WM_STATE only has one Kernel Start Pointer and one GRF Register Count, but we can make the code that handles this on multiple gens simpler if we add an index 0 to it too. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: Add missing field to CLIP_STATE.Rafael Antognolli2017-06-212-0/+5
| | | | | | | | | | | Just because it's not set doesn't mean that it doesn't exist. And since the field is there on newer gens, having it on gen5 simplifies the code when porting gen5 and lower. Also add missing value to API Mode on CLIP_STATE on gen4. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: Fix type of UserClipFlags ClipTest Enable Bitmask.Rafael Antognolli2017-06-213-3/+3
| | | | | | | | This is a bitmask, so it can't be a boolean. Also rename it so it matches gen6+. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: Add missing fields to CLIP_STATE on gen4-5.Rafael Antognolli2017-06-212-0/+2
| | | | | | | | These fields are set by brw_clip_unit, so we need them when converting to genxml. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: Normalize GS_STATE.Rafael Antognolli2017-06-211-1/+1
| | | | | | | Rename "Rendering Enable" to "Rendering Enabled", so it matches gen6+. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: The viewport state offset is actually an address.Rafael Antognolli2017-06-161-1/+1
| | | | | | | This fixes code generation on gen45. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* genxml: Rename fields to match gen6+.Rafael Antognolli2017-06-163-3/+3
| | | | | | | "Anti-aliasing Enable" to "Anti-Aliasing Enable". Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* genxml: Rename SF_STATE field to match gen6+.Rafael Antognolli2017-06-163-9/+9
| | | | | | | | | Rename "Use Point Width State" to "Point Width Source". It accepts the same values and has the same meaning as gen6+, so lets keep them with the same name to simplify the code. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* genxml: Fix Gen4-5 SF_STATE "Line Width" fixed point type.Kenneth Graunke2017-06-143-3/+3
| | | | | | It's a U3.1. It became a U3.7 on Sandybridge. Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: Update genx_bits for gen10+Anuj Phogat2017-06-091-4/+2
| | | | | | | | | | | This commit adds a gen10 case to the switch statement and drops some unneeded code for handling gen numbers which doesn't work on gen10 and above. V2: Drop "z = float(z)" and the "z *= 10" lines Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/cnl: Include gen10_pack.hAnuj Phogat2017-06-091-0/+2
| | | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/cnl: Define genX(x) and GENX(x) for gen10Anuj Phogat2017-06-091-0/+3
| | | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/genxml: Add gen10.xmlJason Ekstrand2017-06-091-0/+3562
| | | | | | | | | | | | | | V2(Anuj): Add default value for length of 3DPRIMITIVE command Add values for 'Attribute Active Component Format' Rename few fields to match gen9.xml V3 (Ander Conselvan de Oliveira) Add gen10 alias for MOCS Make 3DSTATE_CONSTANT_BODY on Gen10 use arrays Signed-off-by: Anuj Phogat <[email protected]> Tested-by: Anuj Phogat <[email protected]>
* genxml: Make 3DSTATE_CONSTANT_BODY on Gen7+ use arrays.Kenneth Graunke2017-06-014-32/+24
| | | | | | This will let us initialize the constant buffers with loops. Reviewed-by: Lionel Landwerlin <[email protected]>
* genxml: Fix parsing of address fields in groups.Kenneth Graunke2017-06-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | For example, <group count="4" start="64" size="64"> <field name="Pointer" start="5" end="63" type="address"/> </group> used to generate: const uint64_t v2_address = __gen_combine_address(data, &dw[2], values->Pointer, 0); ... const uint64_t v4_address = __gen_combine_address(data, &dw[4], values->Pointer, 0); ... but now generates code with proper subscripts: const uint64_t v2_address = __gen_combine_address(data, &dw[2], values->Pointer[0], 0); ... const uint64_t v4_address = __gen_combine_address(data, &dw[4], values->Pointer[1], 0); ... Reviewed-by: Lionel Landwerlin <[email protected]>
* genxml: Add Gen9 CACHE_MODE_1 definitons.Kenneth Graunke2017-05-301-0/+30
| | | | | | | | | These were already in gen8.xml but not gen9.xml. There are a few new fields and a couple that have changed. These are all documented in the Skylake PRM, Volume 2c Command Reference: Registers, Part 1. Reviewed-by: Plamena Manolova <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* genxml: Make a SCISSOR_RECT structure on Gen4-5.Kenneth Graunke2017-05-293-12/+24
| | | | | | | | | | | | | Gen6+ support multiple scissor rectangles, and define a SCISSOR_RECT structure containing their dimensions. On Gen4-5, those same fields exist in SF_VIEWPORT. This patch extracts the SF_VIEWPORT fields into a SCISSOR_RECT structure. Although not a named concept on Gen4-5, it works just as well, and gives us a consistent SCISSOR_RECT structure across all generations, making it easier to reuse code. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/genxml: Rename 3DSTATE_AA_LINE_PARAMS on gen5Jason Ekstrand2017-05-261-1/+1
| | | | | | All of the other gens use "PARAMETERS". Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/genxml: Use the right subtype for VF_STATISTICS on gen4Jason Ekstrand2017-05-261-1/+1
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/genxml: Iron Lake doesn't support non-normalized sampler coordinatesJason Ekstrand2017-05-261-1/+0
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/genxml: Add SAMPLER_STATE to gen 4.5Jason Ekstrand2017-05-261-0/+63
| | | | | | Somehow this got missed. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/genxml: Rename the CC_VIEWPORT pointer on gen4-5Jason Ekstrand2017-05-263-3/+3
| | | | | | | It isn't a pointer to "color calc state", that's the packet it's in. It's a pointer to the CC viewport state. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/genxml: Sampler state is a pointer on gen4-5Jason Ekstrand2017-05-263-9/+9
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/genxml: Suffix KSP0 fields on Iron LakeJason Ekstrand2017-05-261-5/+5
| | | | | | | | | Iron Lake introduced the multiple KSP thing and so you have KSP0-3. However, the genxml didn't have an index on the first "Kernel Start Pointer" or "GRF Register Count". Add one to match gen6+. While we're here, we drop the brackets from the other "GRF Register Count" fields. Reviewed-by: Matt Turner <[email protected]>
* intel/genxml: Make a bunch of things offsets on gen4-5Jason Ekstrand2017-05-263-15/+15
| | | | | | | | | Most things on gen4-5 are addresses because we don't have dynamic state base address and we don't have instruction state base on gen4. However, whoever converted things to addresses got a little over-excited and converted too much. Reviewed-by: Topi Pohjolainen <[email protected]>
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