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* intel/genxml: Add register for object preemption.Rafael Antognolli2018-12-143-0/+24
* genxml: Consistently use a numeric "MOCS" fieldKenneth Graunke2018-12-147-186/+120
* anv/icl: Set use full ways in L3CNTLREGAnuj Phogat2018-11-261-0/+1
* intel/genxml: Add engine definition to render engine instructions (gen11)Toni Lönnberg2018-11-131-116/+116
* intel/genxml: Add engine definition to render engine instructions (gen10)Toni Lönnberg2018-11-131-113/+113
* intel/genxml: Add engine definition to render engine instructions (gen9)Toni Lönnberg2018-11-131-117/+117
* intel/genxml: Add engine definition to render engine instructions (gen8)Toni Lönnberg2018-11-131-116/+116
* intel/genxml: Add engine definition to render engine instructions (gen75)Toni Lönnberg2018-11-131-107/+107
* intel/genxml: Add engine definition to render engine instructions (gen7)Toni Lönnberg2018-11-131-83/+83
* intel/genxml: Add engine definition to render engine instructions (gen6)Toni Lönnberg2018-11-131-54/+54
* intel/genxml: Add engine definition to render engine instructions (gen5)Toni Lönnberg2018-11-131-30/+30
* intel/genxml: Add engine definition to render engine instructions (gen45)Toni Lönnberg2018-11-131-27/+27
* intel/genxml: Add engine definition to render engine instructions (gen4)Toni Lönnberg2018-11-131-25/+25
* anv/icl: Set Error Detection Behavior Control Bit in L3CNTLREGAnuj Phogat2018-11-011-0/+1
* anv/icl: Set Enabled Texel Offset Precision Fix bitAnuj Phogat2018-09-211-0/+5
* intel/genxml: turn SLM Enable bit into booleanLionel Landwerlin2018-09-073-3/+3
* intel: decoder: unify MI_BB_START field namingLionel Landwerlin2018-08-242-6/+6
* anv/icl: Allow headerless sampler messages for pre-emptable contextsAnuj Phogat2018-08-211-0/+5
* intel/genxml: minor python style fixEric Engestrom2018-08-211-1/+1
* intel: various python cleanupsEric Engestrom2018-08-163-17/+14
* meson: Build with Python 3Mathieu Bridon2018-08-101-3/+3
* python: Explicitly use byte stringsMathieu Bridon2018-08-011-2/+2
* python: Open file in binary modeMathieu Bridon2018-08-011-1/+1
* python: Better get character ordinalsMathieu Bridon2018-08-011-2/+2
* python: Better iterate over dictionariesMathieu Bridon2018-07-241-5/+5
* intel/batch_decoder: decoding of 3DSTATE_CONSTANT_BODY.Sergii Romantsov2018-07-161-24/+14
* intel/genxml: Add bitmasks for CS_DEBUG_MODE2/INSTPM.Rafael Antognolli2018-06-187-0/+32
* intel/genxml: Assert that genxml field start and ends are sane.Kenneth Graunke2018-05-071-0/+7
* intel/genxml: Fix some more fake booleans in genxml.Kenneth Graunke2018-05-075-11/+11
* intel/genxml: Make assert in gen_pack_header print a message.Kenneth Graunke2018-05-071-1/+1
* intel/genxml: Fix a few invalid field widthsChris Wilson2018-05-076-28/+28
* intel/genxml: recognize 0x, 0o and 0b when setting default valueCaio Marcelo de Oliveira Filho2018-05-041-1/+2
* intel/genxml: Add Clear Color struct to gen10+.Rafael Antognolli2018-04-052-0/+18
* intel/genxml: Use a single field for clear color address on gen10.Rafael Antognolli2018-04-052-8/+6
* genxml: Preserve fields that share dword space with addresses.Rafael Antognolli2018-04-051-2/+6
* intel: genxml: decode variable length MI_LRILionel Landwerlin2018-04-0310-0/+40
* intel: genxml: add preemption control instructionsLionel Landwerlin2018-04-034-0/+26
* intel/genxml: Add SAMPLER_INSTDONE register.Rafael Antognolli2018-03-266-0/+139
* intel/genxml: Add ROW_INSTDONE register.Rafael Antognolli2018-03-266-0/+114
* intel/genxml: Add SC_INSTDONE register.Rafael Antognolli2018-03-266-0/+140
* intel: genxml: add INSTPM/CS_DEBUG_MODE2 registersLionel Landwerlin2018-03-207-0/+46
* intel: Drop SURFACE_FORMAT enum from genxml.Kenneth Graunke2018-03-0510-2251/+17
* intel: Split gen_device_info out into libintel_devJordan Justen2018-03-051-1/+1
* genxml: Silence unused parameter warnings in generated pack codeIan Romanick2018-03-021-3/+11
* intel/genxml/icl: Update genx_bits headerAnuj Phogat2018-02-151-0/+1
* intel/genxml/icl: Generate packing headersAnuj Phogat2018-02-153-0/+6
* intel/genxml/icl: Add gen11.xmlAnuj Phogat2018-02-151-0/+3765
* meson: don't use intermediate variables that are immediately discardedDylan Baker2018-01-111-2/+1
* genxml: Add missing INSTDONE_1 bits on Gen7.5+.Kenneth Graunke2018-01-094-0/+8
* intel: Apply Geminilake "Barrier Mode" workaround.Kenneth Graunke2018-01-091-0/+8
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