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* intel/genxml: Add patch count threshold field on gen12Sagar Ghuge2020-03-231-0/+1
| | | | | | Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3563>
* intel/gen12+: Disable mid thread preemption.Rafael Antognolli2020-03-031-0/+1
| | | | | | | | | | | | | Fixes a GPU hang in Car Chase. Cc: [email protected] v2: Add comment explaining why (Jason). Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4035> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4035>
* intel/isl: Implement D16_UNORM workarounds.Rafael Antognolli2020-03-031-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | GEN:BUG:14010455700 (lineage 1808121037): "To avoid sporadic corruptions “Set 0x7010[9] when Depth Buffer Surface Format is D16_UNORM , surface type is not NULL & 1X_MSAA" Required for fixing ttps://gitlab.freedesktop.org/mesa/mesa/issues/2501. GEN:BUG:1806527549: "Set HIZ_CHICKEN (7018h) bit 13 = 1 when depth buffer is D16_UNORM." This one could fix a GPU hang in some workloads. v2: Implement WA in isl and add another similar WA (Jason). v3: Add flushes before changing chicken registers (Jason) v4: Depth flush and stall + end of pipe sync when changing registers (Jason). Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3801> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3801>
* intel/genxml: Drop "reserved" enumKenneth Graunke2020-02-051-1/+0
| | | | | | | | | | | This was adding "#define reserved 2" to genxml includes, which is a fairly mean lowercase word to redefine. It ends up breaking the build on Android, which has __u32 reserved fields in headers. Defining it also has no purpose. Just drop it. Fixes: 5bea0cf7795 ("intel/isl: Move iris's pipe-to-isl format function to isl.") Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3729>
* intel/genxml: Drop SLMEnable from L3CNTLREG on Gen11Jason Ekstrand2020-01-301-1/+0
| | | | | | | | | | | | SML is no longer in the L3$ on Gen11+. It's not incredibly clear from the docs but no Gen11 platforms are in the list of platforms on which this bit exists. Also, we've been always setting it false on Gen11 in ANV and i965 thanks to GEN_L3P_SLM being zero with no ill effects. Cc: "20.0" [email protected] Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
* genxml: Add a new 3DSTATE_SF field on gen12Jason Ekstrand2020-01-301-0/+5
| | | | | | | Cc: [email protected] Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
* intel/genxml: Make SO_DECL::"Hole Flag" a BooleanJason Ekstrand2020-01-277-7/+7
| | | | | Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3520>
* genxml: add new Gen11+ PIPE_CONTROL fieldLionel Landwerlin2020-01-162-0/+2
| | | | | | | | | PIPE_CONTROL gained a new field in its first DWORD on Gen11. We had no use for it so far, but we start using it on Gen12. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3408>
* genxml: Remove a non-existant HW bitJason Ekstrand2020-01-093-3/+0
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* intel/genxml: Add a partial TCCNTLREG definitionKenneth Graunke2019-12-101-0/+7
| | | | | | | TCCNTLREG contains additional cache programming settings. In particular, there are several write combining controls we'd like to use. Acked-by: Jason Ekstrand <[email protected]>
* intel/genxml: Add 3DSTATE_CONSTANT_ALL packet.Rafael Antognolli2019-12-041-0/+25
| | | | Acked-by: Caio Marcelo de Oliveira Filho <[email protected]>
* genxml: Mark everything in genX_pack.h always_inlineJason Ekstrand2019-11-181-8/+8
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Add gen12 tile cache flush bitJordan Justen2019-10-301-0/+1
| | | | Signed-off-by: Jordan Justen <[email protected]>
* genxml/gen12: Add Stencil Buffer Resolve Enable bitSagar Ghuge2019-10-291-0/+1
| | | | | Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* genxml: Add 3DSTATE_SO_BUFFER_INDEX_* instructionsPlamena Manolova2019-10-291-0/+47
| | | | | | | | For gen12 we set the streamout buffers using 4 separate commands instead of 3DSTATE_SO_BUFFER. Signed-off-by: Plamena Manolova <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* genxml: Change 3DSTATE_DEPTH_BOUNDS bias.Plamena Manolova2019-10-291-1/+1
| | | | | | | | | The bias for the 3DSTATE_DEPTH_BOUNDS instruction should be 2 not 1. Signed-off-by: Plamena Manolova <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* intel: Fix and use HIZ_CCS write through modeNanley Chery2019-10-281-0/+1
| | | | | | | | Write through to the CCS if the surface is used as a texture and can be sampled by the HW with CCS. Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Use 3DSTATE_DEPTH_BUFFER::ControlSurfaceEnableNanley Chery2019-10-281-0/+1
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Use RENDER_SURFACE_STATE::DepthStencilResourceNanley Chery2019-10-281-0/+1
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/blorp/gen12: Set FWCC when storing the clear color.Rafael Antognolli2019-10-281-0/+1
| | | | | | | | | | | | | | | | | | | | From "Render Target Fast Clear" description for Gen12: "SW must store clear color using MI_STORE_DATA_IMM with ForceWriteCompletionCheck bit set." From Instruction_MI_STORE_DATA_IMM, bitfield 10 (when set to 1): "Following the last write from this command, Command Streamer will wait for all previous writes are completed and in global observable domain before moving to next command." We use 4 SDIs to store the clear color (one per channel). From the description, it looks to me that setting that flag only on the last SDI should be enough. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* genxml: Add 3DSTATE_DEPTH_BOUNDS instruction.Plamena Manolova2019-10-281-0/+13
| | | | | | | | In gen12 we add the 3DSTATE_DEPTH_BOUNDS instruction which enables support for depth bounds testing. Signed-off-by: Plamena Manolova <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml/gen12: Add AUX MAP register definitionsJordan Justen2019-10-281-0/+8
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: add RPSTAT register for core frequencyLionel Landwerlin2019-10-238-0/+40
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: add generic perf counters registersLionel Landwerlin2019-10-234-0/+72
| | | | | | | | | | We have 2 of those we can configure to source programmable events. Those are not part of the OA reports. Configuration happens in i915 through the metric set selected by the application. On the Mesa side we'll just sample those and do a diff. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: Remove W-tiling on gen12Jason Ekstrand2019-10-171-1/+0
| | | | | | It's no longer supported by the hardware Reviewed-by: Nanley Chery <[email protected]>
* intel/genxml,isl: Add gen12 stencil buffer changesJordan Justen2019-10-171-5/+30
| | | | | | | | | Rework: * NULL stencil buffer path (Jason) * genxml fixes (Nanley) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/genxml,isl: Add gen12 depth buffer changesJordan Justen2019-10-171-9/+13
| | | | | | | | | Reworks: * Fix 3DSTATE_DEPTH_BUFFER "Surface Format" end in xml (Jason) * Remove WM_HZ_OP changes (Nanley) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/genxml,isl: Add gen12 render surface state changesJordan Justen2019-10-171-10/+9
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/genxml: Stop manually scrubbing 'α' -> "alpha"Kenneth Graunke2019-09-232-2/+1
| | | | | | | 'α' has never appeared in any genxml files, so there's no need to replace it with the word "alpha". Reviewed-by: Jordan Justen <[email protected]>
* genxml/gen11+: Add COMMON_SLICE_CHICKEN4 registerAnuj Phogat2019-09-112-0/+10
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* anv,iris: L3ALLOC register replaces L3CNTLREG for gen12Jordan Justen2019-09-061-4/+3
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: Build gen12 genxmlJordan Justen2019-08-284-0/+7
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Add gen12.xml as a copy of gen11.xmlJordan Justen2019-08-281-0/+7171
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Run sort_xml.sh to tidy gen9.xml and gen11.xmlJordan Justen2019-08-282-38/+36
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml/gen11: Add spaces in EnableUnormPathInColorPipeJordan Justen2019-08-281-1/+1
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Handle field names with different spacing/hyphenJordan Justen2019-08-281-3/+4
| | | | | | | | | | | | | If a field name differs slightly between two generations then this change will still add the fields into the same group. For example, these will be treated as equal: * "Software Exception" and "Software Exception" * "Per Thread" and "Per-Thread" Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* isl: Enable Unorm Path in Color PipeKenneth Graunke2019-08-151-0/+1
| | | | | | | | | | | | | | | | Improves performance on my Icelake 8x8 locked to 700Mhz. For example, some GfxBench5 subtests have the following results: - [i965] gl_manhattan: ................ 7.01119% +/- 0.180971% (n=5) - [i965] gl_4 (Car Chase): 4.24351% +/- 0.175622% (n=5) - [i965] gl_blending: ................ 3.36327% +/- 0.180267% (n=5) - [i965] gl_5_normal (Aztec Ruins): 1.67962% +/- 0.243534% (n=10) - [iris] gl_manhattan: ................ 3.92357% +/- 0.073965% (n=25) - [iris] gl_4 (Car Chase): 2.17746% +/- 0.0826858% (n=5) - [iris] gl_blending: ................ 2.79599% +/- 0.803652% (n=15) - [iris] gl_5_normal (Aztec Ruins): 1.30930% +/- 0.106523% (n=25) Reviewed-by: Jason Ekstrand <[email protected]>
* intel/genxml: Update 3D_MODE and add SLICE_HASH_TABLE.Rafael Antognolli2019-08-121-1/+33
| | | | | | | Add these fields and the 3DSTATE_SLICE_TABLE_STATE_POINTERS instruction so we can properly configure the slice and subslice hashing on ICL+ v2: Make 'Mask' field a mbo (Ken).
* intel/genxml: Add GT_MODE hashing defs for Gen9.Francisco Jerez2019-08-121-0/+17
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Rename 3DSTATE_SF::Anti-Aliasing EnableJason Ekstrand2019-08-066-6/+6
| | | | | | | This makes it consistent with the new name when it's moved to 3DSTATE_RASTER. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Add basic infra for encoding/decoding unit tests.Rafael Antognolli2019-07-231-0/+2
| | | | | | | | Adding option to print quiet. v2: Add license header. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: correct bit fields in CACHE_MODE_0 reg for gen11Dongwon Kim2019-07-081-16/+14
| | | | | | | correct bit fields information of CACHE_MODE_0 reg in current gen11.xml Signed-off-by: Dongwon Kim <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* intel/genxml: Update MI_ATOMIC genxml definition.Rafael Antognolli2019-04-293-15/+117
| | | | | | | Change some of the single bit fields to booleans, and add an enum with the definition of the ATOMIC_OPCODE. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Support base-16 in value & start fields in gen_sort_tags.pyJordan Justen2019-04-291-2/+2
| | | | | | | | With python's int(), if the optional second parameter is 0, then python will support the 0x prefix for hex numbers. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* delete autotools .gitignore filesEric Engestrom2019-04-291-3/+0
| | | | | | | | One special case, `src/util/xmlpool/.gitignore` is not entirely deleted, as `xmlpool.pot` still gets generated (eg. by `ninja xmlpool-pot`). Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* iris: implement WaEnableStateCacheRedirectToCSLionel Landwerlin2019-04-181-0/+5
| | | | | | | | | | | | This 3d performance workaround was initially put in the kernel but the media driver requires different settings so the register has been whitelisted in i915 [1] and userspace drivers are left initializing it as they wish. [1] : https://patchwork.freedesktop.org/series/59494/ Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* genxml: sort xml files using new scriptLionel Landwerlin2019-04-0910-21155/+21105
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* genxml: add a sorting scriptLionel Landwerlin2019-04-093-0/+203
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: add dependency on genxml generated filesLionel Landwerlin2019-04-081-0/+2
| | | | | | | | | | Drivers using genxml will start compilation before generated files are created, so add a dependency to it. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]> Cc: [email protected]
* intel/genxml: Media instructions and structures for gen11Toni Lönnberg2019-03-281-24/+3450
| | | | | | | | | | | v2: Lionel Landwerlin <[email protected]> - fix missing type - fix *_FQM_*/*_QM_* commands - shorten some media structs using groups - factor out memory attributes - switch MI_FLUSH_DW fields to bool Reviewed-by: Lionel Landwerlin <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-02 18:58:59 +0000