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path: root/src/intel/genxml
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* intel: various python cleanupsEric Engestrom2018-08-163-17/+14
* meson: Build with Python 3Mathieu Bridon2018-08-101-3/+3
* python: Explicitly use byte stringsMathieu Bridon2018-08-011-2/+2
* python: Open file in binary modeMathieu Bridon2018-08-011-1/+1
* python: Better get character ordinalsMathieu Bridon2018-08-011-2/+2
* python: Better iterate over dictionariesMathieu Bridon2018-07-241-5/+5
* intel/batch_decoder: decoding of 3DSTATE_CONSTANT_BODY.Sergii Romantsov2018-07-161-24/+14
* intel/genxml: Add bitmasks for CS_DEBUG_MODE2/INSTPM.Rafael Antognolli2018-06-187-0/+32
* intel/genxml: Assert that genxml field start and ends are sane.Kenneth Graunke2018-05-071-0/+7
* intel/genxml: Fix some more fake booleans in genxml.Kenneth Graunke2018-05-075-11/+11
* intel/genxml: Make assert in gen_pack_header print a message.Kenneth Graunke2018-05-071-1/+1
* intel/genxml: Fix a few invalid field widthsChris Wilson2018-05-076-28/+28
* intel/genxml: recognize 0x, 0o and 0b when setting default valueCaio Marcelo de Oliveira Filho2018-05-041-1/+2
* intel/genxml: Add Clear Color struct to gen10+.Rafael Antognolli2018-04-052-0/+18
* intel/genxml: Use a single field for clear color address on gen10.Rafael Antognolli2018-04-052-8/+6
* genxml: Preserve fields that share dword space with addresses.Rafael Antognolli2018-04-051-2/+6
* intel: genxml: decode variable length MI_LRILionel Landwerlin2018-04-0310-0/+40
* intel: genxml: add preemption control instructionsLionel Landwerlin2018-04-034-0/+26
* intel/genxml: Add SAMPLER_INSTDONE register.Rafael Antognolli2018-03-266-0/+139
* intel/genxml: Add ROW_INSTDONE register.Rafael Antognolli2018-03-266-0/+114
* intel/genxml: Add SC_INSTDONE register.Rafael Antognolli2018-03-266-0/+140
* intel: genxml: add INSTPM/CS_DEBUG_MODE2 registersLionel Landwerlin2018-03-207-0/+46
* intel: Drop SURFACE_FORMAT enum from genxml.Kenneth Graunke2018-03-0510-2251/+17
* intel: Split gen_device_info out into libintel_devJordan Justen2018-03-051-1/+1
* genxml: Silence unused parameter warnings in generated pack codeIan Romanick2018-03-021-3/+11
* intel/genxml/icl: Update genx_bits headerAnuj Phogat2018-02-151-0/+1
* intel/genxml/icl: Generate packing headersAnuj Phogat2018-02-153-0/+6
* intel/genxml/icl: Add gen11.xmlAnuj Phogat2018-02-151-0/+3765
* meson: don't use intermediate variables that are immediately discardedDylan Baker2018-01-111-2/+1
* genxml: Add missing INSTDONE_1 bits on Gen7.5+.Kenneth Graunke2018-01-094-0/+8
* intel: Apply Geminilake "Barrier Mode" workaround.Kenneth Graunke2018-01-091-0/+8
* genxml: fix assert guardsEric Engestrom2017-11-231-5/+5
* intel/genxml: Add helpers for determining field typeKristian H. Kristensen2017-11-211-6/+17
* genxml: Fix PIPELINE_SELECT on G45/Ironlake.Kenneth Graunke2017-11-162-2/+2
* intel/genxml: Add Cache Mode SubSlice Register to gen10.xmlAnuj Phogat2017-11-141-0/+12
* intel/genxml: Delete empty groupsJason Ekstrand2017-11-134-8/+0
* intel: Make Cube Face Enable fields consistent across generations.Kenneth Graunke2017-10-036-6/+36
* meson: Add build Intel "anv" vulkan driverDylan Baker2017-09-271-0/+59
* intel/genxml: Convert a not-present-or-"1" dict to a set.Eric Anholt2017-09-261-2/+3
* genxml: Make Border Color Pointer an address on Gen4-5, not an offset.Kenneth Graunke2017-09-023-3/+3
* intel/genxml: Fix gen10 BLEND_STATE variable length packingScott D Phillips2017-08-151-2/+2
* intel: genxml: make a couple of enums show up in aubinatorLionel Landwerlin2017-07-026-45/+47
* genxml: Silence about a billion unused parameter warningsIan Romanick2017-06-281-2/+7
* genxml: fix gen5 sampler border color state.Rafael Antognolli2017-06-221-20/+20
* intel/genxml: Add Gen10 CACHE_MODE_1 definitionsAnuj Phogat2017-06-221-0/+18
* intel/genxml: Rename StartInstanceLocation to StartingInstanceLocationAnuj Phogat2017-06-221-1/+1
* intel/genxml: Rename IndirectStatePointer to BorderColorPointerAnuj Phogat2017-06-221-1/+1
* intel/genxml: Combine DataDWord{0, 1} fields in to ImmediateData fieldAnuj Phogat2017-06-221-2/+1
* intel/genxml: Add INSTDONE registers in gen10Anuj Phogat2017-06-221-0/+115
* intel/genxml: Add better support for MI_MATH in gen10Anuj Phogat2017-06-221-4/+65
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