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* intel/genxml: add RPSTAT register for core frequencyLionel Landwerlin2019-10-231-0/+5
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: add generic perf counters registersLionel Landwerlin2019-10-231-0/+18
| | | | | | | | | | We have 2 of those we can configure to source programmable events. Those are not part of the OA reports. Configuration happens in i915 through the metric set selected by the application. On the Mesa side we'll just sample those and do a diff. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: Run sort_xml.sh to tidy gen9.xml and gen11.xmlJordan Justen2019-08-281-17/+17
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Add GT_MODE hashing defs for Gen9.Francisco Jerez2019-08-121-0/+17
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: Update MI_ATOMIC genxml definition.Rafael Antognolli2019-04-291-5/+39
| | | | | | | Change some of the single bit fields to booleans, and add an enum with the definition of the ATOMIC_OPCODE. Reviewed-by: Lionel Landwerlin <[email protected]>
* genxml: sort xml files using new scriptLionel Landwerlin2019-04-091-3575/+3570
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* intel/genxml: Media instructions and structures for gen9Toni Lönnberg2019-03-281-24/+3090
| | | | | | | | | | | v2: Lionel Landwerlin <[email protected]> - fix missing type - fix *_FQM_*/*_QM_* commands - shorten some media structs using groups - factor out memory attributes - switch MI_FLUSH_DW fields to bool Reviewed-by: Lionel Landwerlin <[email protected]>
* genxml: add missing field values for 3DSTATE_SFJuan A. Suarez Romero2019-02-221-1/+4
| | | | | | | | | Fill out "Vertex Sub Pixel Precision Select" possible values. CC: 18.3 19.0 <[email protected]> Signed-off-by: Juan A. Suarez Romero <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* genxml: Add SO_PRIM_STORAGE_NEEDED and SO_NUM_PRIMS_WRITTENJason Ekstrand2019-01-221-0/+32
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: add missing MI_PREDICATE compare operationsLionel Landwerlin2019-01-191-0/+2
| | | | | | | | Doesn't save us a great deal of lines but at least they get decoded in aubinators. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: Add register for object preemption.Rafael Antognolli2018-12-141-0/+8
| | | | | Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Consistently use a numeric "MOCS" fieldKenneth Graunke2018-12-141-31/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When we first started using genxml, we decided to represent MOCS as an actual structure, and pack values. However, in many places, it was more convenient to use a numeric value rather than treating it as a struct, so we added secondary setters in a bunch of places as well. We were not entirely consistent, either. Some places only had one. Gen6 had both kinds of setters for STATE_BASE_ADDRESS, but newer gens only had the struct-based setters. The names were sometimes "Constant Buffer Object Control State" instead of "Memory", making it harder to find. Many had prefixes like "Vertex Buffer MOCS"...in a vertex buffer packet...which is a bit redundant. On modern hardware, MOCS is simply an index into a table, but we were still carrying around the structure with an "Index to MOCS Table" field, in addition to the direct numeric setters. This is clunky - we really just want a number on new hardware. This patch eliminates the struct-based setters, and makes the numeric setters be consistently called "MOCS". We leave the struct definition around on Gen7-8 for reference purposes, but it is unused. v2: Drop bonus "Depth Buffer MOCS" fields on Gen7.5 and Gen9 Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* intel/genxml: Add engine definition to render engine instructions (gen9)Toni Lönnberg2018-11-131-117/+117
| | | | | | | | | | | | | | Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added more missing engine definitions. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: turn SLM Enable bit into booleanLionel Landwerlin2018-09-071-1/+1
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/genxml: Add bitmasks for CS_DEBUG_MODE2/INSTPM.Rafael Antognolli2018-06-181-0/+4
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Fix some more fake booleans in genxml.Kenneth Graunke2018-05-071-2/+2
| | | | | | | | | None of these are actually booleans. Tile Parameter is a tiling mode enum. Display pipes take plane numbers. Predicate Enable has some operations (and the default value of 6 was particular bogus). Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel: genxml: decode variable length MI_LRILionel Landwerlin2018-04-031-0/+4
| | | | | | | | | | | | | | | MI_LOAD_REGISTER_IMM can load multiple (register, value) tuples in one command. In our drivers we only use one tuple at a time, but the kernel might load more than one at a time. Instead of making all the tuple part of a group, we leave out the first tuple (the one we use in the generated packing structures). This is particularly useful for looking at error stats generated by the kernel. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* intel: genxml: add preemption control instructionsLionel Landwerlin2018-04-031-0/+6
| | | | | | | Helpful to debug kernel workaround batchbuffers. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* intel/genxml: Add SAMPLER_INSTDONE register.Rafael Antognolli2018-03-261-0/+23
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Add ROW_INSTDONE register.Rafael Antognolli2018-03-261-0/+18
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Add SC_INSTDONE register.Rafael Antognolli2018-03-261-0/+26
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* intel: genxml: add INSTPM/CS_DEBUG_MODE2 registersLionel Landwerlin2018-03-201-0/+6
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Drop SURFACE_FORMAT enum from genxml.Kenneth Graunke2018-03-051-226/+2
| | | | | | | | | | | We want people to be using ISL_FORMAT_*, rather than the genxml format enumerations. This patch drops 10 separate copies, and drops a bunch of ugly casting. Reviewed-by: Jordan Justen <[email protected]> [[email protected]: Minor changes for rebase] Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* genxml: Add missing INSTDONE_1 bits on Gen7.5+.Kenneth Graunke2018-01-091-0/+2
| | | | | | This will make aubinator_error_decode decode them properly. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel: Apply Geminilake "Barrier Mode" workaround.Kenneth Graunke2018-01-091-0/+8
| | | | | | | | | | | | | | | | | | | Apparently, Geminilake requires you to whack a chicken bit to select either compute or tessellation mode for barriers. The recommendation is to switch between them at PIPELINE_SELECT time. We may not need to do this all the time, but I don't know that it hurts either. PIPELINE_SELECT is already a pretty giant stall. This appears to fix hangs in tessellation control shaders with barriers on Geminilake. Note that this requires a corresponding kernel change, drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake. in order for the register write to actually happen. Without an updated kernel, this register write will be noop'd and the fix will not work. Reviewed-by: Rafael Antognolli <[email protected]>
* intel: genxml: make a couple of enums show up in aubinatorLionel Landwerlin2017-07-021-7/+7
| | | | | | | In particular Shader Channel Select & Texture Address Control Mode. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* genxml: Make 3DSTATE_CONSTANT_BODY on Gen7+ use arrays.Kenneth Graunke2017-06-011-8/+6
| | | | | | This will let us initialize the constant buffers with loops. Reviewed-by: Lionel Landwerlin <[email protected]>
* genxml: Add Gen9 CACHE_MODE_1 definitons.Kenneth Graunke2017-05-301-0/+30
| | | | | | | | | These were already in gen8.xml but not gen9.xml. There are a few new fields and a couple that have changed. These are all documented in the Skylake PRM, Volume 2c Command Reference: Registers, Part 1. Reviewed-by: Plamena Manolova <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* genxml: Add alias for MOCS.Rafael Antognolli2017-05-111-0/+1
| | | | | | | | Use an alias for this field on 3DSTATE_INDEX_BUFFER on gen6+, so we can set the same value as the defines. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* genxml: Rename "Function Enable" to "Enable".Rafael Antognolli2017-05-031-3/+3
| | | | | | | | | | Rename that field name on genxml for: - 3DSTATE_GS - gen6+ - 3DSTATE_DS - gen7+ - 3DSTATE_HS - gen7+ Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: 3DSTATE_VS rename Function Enable to Enable.Rafael Antognolli2017-05-031-1/+1
| | | | | Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Add alias for MOCS.Rafael Antognolli2017-05-031-0/+1
| | | | | | | | | | | Use an alias, so we can set the same value as the #define's. v3: - Call it "SO Buffer MOCS" to follow the most common naming scheme. - Add alias for gen7 and gen75 too (Ken). Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Add missing field values to 3DSTATE_SBE.Rafael Antognolli2017-05-031-1/+6
| | | | | | | Fill out "Attribute Active Component Format" possible values. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Make BLEND_STATE command support variable length array.Rafael Antognolli2017-04-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | We need to emit BLEND_STATE, which size is 1 + 2 * nr_draw_buffers dwords (on gen8+), but the BLEND_STATE struct length is always 17. By marking it size 1, which is actually the size of the struct minus the BLEND_STATE_ENTRY's, we can emit a BLEND_STATE of variable number of entries. For gen6 and gen7 we set length to 0, since it only contains BLEND_STATE_ENTRY's, and no other data. With this change, we also change the code for blorp and anv to emit only the needed BLEND_STATE_ENTRY's, instead of always emitting 16 dwords on gen6-7 and 17 dwords on gen8+. v2: - Use designated initializers on blorp and remove 0 from initialization (Jason) - Default entries to disabled on Vulkan (Jason) - Rebase code. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Add better support for MI_MATHJason Ekstrand2017-04-201-4/+65
| | | | | | | | This breaks the guts of MI_MATH (the instruction part) out into its own structure with proper named values. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed by: Iago Toral Quiroga <[email protected]>
* intel: genxml: add RING_BUFFER_CTL registersLionel Landwerlin2017-04-041-0/+69
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel: genxml: add FAULT_REG registerLionel Landwerlin2017-04-041-0/+23
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel: genxml: add ACTHD registersLionel Landwerlin2017-04-041-0/+16
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel: genxml: add GFX_ARB_ERROR_RPT registerLionel Landwerlin2017-04-041-0/+18
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel: genxml: add INSTDONE registersLionel Landwerlin2017-04-041-0/+71
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* genxml: Whitespace fixesJason Ekstrand2017-03-241-4/+4
| | | | | | | Some field names had extra spaces and some had places where we should have had a space but didn't. Reviewed-by: Chad Versace <[email protected]>
* genxml: Make MI_STORE_DATA_IMM have a single 64-bit data fieldJason Ekstrand2017-03-171-2/+1
| | | | | | This is way more convenient than having two separate dword fields. Reviewed-By: Lionel Landwerlin <[email protected]>
* genxml: s/Clipper Statistics Enable/Statistics Enable/Jason Ekstrand2017-03-171-1/+1
| | | | | | | It's in 3DSTATE_CLIP, so it doesn't really need the extra detail. This matches what we do for VS, FS, etc. Reviewed-by: Lionel Landwerlin <[email protected]>
* genxml: Add pipeline statistics registers on gen7+Jason Ekstrand2017-03-171-0/+44
| | | | Reviewed-By: Lionel Landwerlin <[email protected]>
* genxml: Add XML version tagsJason Ekstrand2017-03-161-0/+1
| | | | | | | There's not much point to having them or not having them but this reduces some pointless diff from the version we can auto-generate Reviewed-by: Lionel Landwerlin <[email protected]>
* genxml: Add the CACHE_MODE_0 register on gen9Jason Ekstrand2017-02-141-0/+28
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* genxml: Rename 3DSTATE_HS::Enable to "Function Enable".Kenneth Graunke2017-01-101-1/+1
| | | | | | | "Function Enable" is what the other stages use. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* genxml/gen9: Change the default of MI_SEMAPHORE_WAIT::RegisterPoleModeJason Ekstrand2016-12-061-1/+1
| | | | | | | | | | We would really like it to be false as that's what you get on hardware that doesn't have RegisterPoleMode (Sky Lake for example). While we're at it, we change it to a boolean. This fixes dEQP-VK.synchronization.smoke.events on Broxton. Reviewed-by: Kenneth Graunke <[email protected]> Cc: "13.0" <[email protected]>
* intel/genxml: Fix ksp for INTERFACE_DESCRIPTOR_DATAKristian H. Kristensen2016-11-291-2/+1
| | | | | | | | | | This one was split across two dwords as "Kernel Start Pointer" and "Kernel Start Pointer High", which looks like it works when the driver only accesses "Kernel Start Pointer". This breaks, of course, with BO offsets > 4G. Signed-off-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/genxml: Use enum 3D_Logic_Op_Function where applicableKristian H. Kristensen2016-11-291-1/+1
| | | | | Signed-off-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
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