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path: root/src/intel/genxml/gen9.xml
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* genxml: fix invalid end value for video fieldsLionel Landwerlin2020-05-091-1/+1
* intel/genxml: Make SO_DECL::"Hole Flag" a BooleanJason Ekstrand2020-01-271-1/+1
* intel/genxml: add RPSTAT register for core frequencyLionel Landwerlin2019-10-231-0/+5
* intel/genxml: add generic perf counters registersLionel Landwerlin2019-10-231-0/+18
* intel/genxml: Run sort_xml.sh to tidy gen9.xml and gen11.xmlJordan Justen2019-08-281-17/+17
* intel/genxml: Add GT_MODE hashing defs for Gen9.Francisco Jerez2019-08-121-0/+17
* intel/genxml: Update MI_ATOMIC genxml definition.Rafael Antognolli2019-04-291-5/+39
* genxml: sort xml files using new scriptLionel Landwerlin2019-04-091-3575/+3570
* intel/genxml: Media instructions and structures for gen9Toni Lönnberg2019-03-281-24/+3090
* genxml: add missing field values for 3DSTATE_SFJuan A. Suarez Romero2019-02-221-1/+4
* genxml: Add SO_PRIM_STORAGE_NEEDED and SO_NUM_PRIMS_WRITTENJason Ekstrand2019-01-221-0/+32
* intel/genxml: add missing MI_PREDICATE compare operationsLionel Landwerlin2019-01-191-0/+2
* intel/genxml: Add register for object preemption.Rafael Antognolli2018-12-141-0/+8
* genxml: Consistently use a numeric "MOCS" fieldKenneth Graunke2018-12-141-31/+20
* intel/genxml: Add engine definition to render engine instructions (gen9)Toni Lönnberg2018-11-131-117/+117
* intel/genxml: turn SLM Enable bit into booleanLionel Landwerlin2018-09-071-1/+1
* intel/genxml: Add bitmasks for CS_DEBUG_MODE2/INSTPM.Rafael Antognolli2018-06-181-0/+4
* intel/genxml: Fix some more fake booleans in genxml.Kenneth Graunke2018-05-071-2/+2
* intel: genxml: decode variable length MI_LRILionel Landwerlin2018-04-031-0/+4
* intel: genxml: add preemption control instructionsLionel Landwerlin2018-04-031-0/+6
* intel/genxml: Add SAMPLER_INSTDONE register.Rafael Antognolli2018-03-261-0/+23
* intel/genxml: Add ROW_INSTDONE register.Rafael Antognolli2018-03-261-0/+18
* intel/genxml: Add SC_INSTDONE register.Rafael Antognolli2018-03-261-0/+26
* intel: genxml: add INSTPM/CS_DEBUG_MODE2 registersLionel Landwerlin2018-03-201-0/+6
* intel: Drop SURFACE_FORMAT enum from genxml.Kenneth Graunke2018-03-051-226/+2
* genxml: Add missing INSTDONE_1 bits on Gen7.5+.Kenneth Graunke2018-01-091-0/+2
* intel: Apply Geminilake "Barrier Mode" workaround.Kenneth Graunke2018-01-091-0/+8
* intel: genxml: make a couple of enums show up in aubinatorLionel Landwerlin2017-07-021-7/+7
* genxml: Make 3DSTATE_CONSTANT_BODY on Gen7+ use arrays.Kenneth Graunke2017-06-011-8/+6
* genxml: Add Gen9 CACHE_MODE_1 definitons.Kenneth Graunke2017-05-301-0/+30
* genxml: Add alias for MOCS.Rafael Antognolli2017-05-111-0/+1
* genxml: Rename "Function Enable" to "Enable".Rafael Antognolli2017-05-031-3/+3
* genxml: 3DSTATE_VS rename Function Enable to Enable.Rafael Antognolli2017-05-031-1/+1
* genxml: Add alias for MOCS.Rafael Antognolli2017-05-031-0/+1
* genxml: Add missing field values to 3DSTATE_SBE.Rafael Antognolli2017-05-031-1/+6
* genxml: Make BLEND_STATE command support variable length array.Rafael Antognolli2017-04-241-2/+2
* genxml: Add better support for MI_MATHJason Ekstrand2017-04-201-4/+65
* intel: genxml: add RING_BUFFER_CTL registersLionel Landwerlin2017-04-041-0/+69
* intel: genxml: add FAULT_REG registerLionel Landwerlin2017-04-041-0/+23
* intel: genxml: add ACTHD registersLionel Landwerlin2017-04-041-0/+16
* intel: genxml: add GFX_ARB_ERROR_RPT registerLionel Landwerlin2017-04-041-0/+18
* intel: genxml: add INSTDONE registersLionel Landwerlin2017-04-041-0/+71
* genxml: Whitespace fixesJason Ekstrand2017-03-241-4/+4
* genxml: Make MI_STORE_DATA_IMM have a single 64-bit data fieldJason Ekstrand2017-03-171-2/+1
* genxml: s/Clipper Statistics Enable/Statistics Enable/Jason Ekstrand2017-03-171-1/+1
* genxml: Add pipeline statistics registers on gen7+Jason Ekstrand2017-03-171-0/+44
* genxml: Add XML version tagsJason Ekstrand2017-03-161-0/+1
* genxml: Add the CACHE_MODE_0 register on gen9Jason Ekstrand2017-02-141-0/+28
* genxml: Rename 3DSTATE_HS::Enable to "Function Enable".Kenneth Graunke2017-01-101-1/+1
* genxml/gen9: Change the default of MI_SEMAPHORE_WAIT::RegisterPoleModeJason Ekstrand2016-12-061-1/+1
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