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* genxml: Make MI_STORE_DATA_IMM have a single 64-bit data fieldJason Ekstrand2017-03-171-2/+1
| | | | | | This is way more convenient than having two separate dword fields. Reviewed-By: Lionel Landwerlin <[email protected]>
* genxml: s/Clipper Statistics Enable/Statistics Enable/Jason Ekstrand2017-03-171-1/+1
| | | | | | | It's in 3DSTATE_CLIP, so it doesn't really need the extra detail. This matches what we do for VS, FS, etc. Reviewed-by: Lionel Landwerlin <[email protected]>
* genxml: Add pipeline statistics registers on gen7+Jason Ekstrand2017-03-171-0/+44
| | | | Reviewed-By: Lionel Landwerlin <[email protected]>
* genxml: Add XML version tagsJason Ekstrand2017-03-161-0/+1
| | | | | | | There's not much point to having them or not having them but this reduces some pointless diff from the version we can auto-generate Reviewed-by: Lionel Landwerlin <[email protected]>
* genxml: Make MI_STORE_DATA_IMM more consistentJason Ekstrand2017-02-211-1/+1
| | | | | Reviewed-by: Lionel Landwerlin <[email protected]> Cc: "13.0 17.0" <[email protected]>
* genxml: Rename 3DSTATE_HS::Enable to "Function Enable".Kenneth Graunke2017-01-101-1/+1
| | | | | | | "Function Enable" is what the other stages use. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* genxml: Rename "DS Function Enable" to "Function Enable".Kenneth Graunke2016-12-141-1/+1
| | | | | | | This makes Gen7/7.5 match Gen8-9. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Use enum 3D_Logic_Op_Function where applicableKristian H. Kristensen2016-11-291-18/+20
| | | | | Signed-off-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/genxml: Use blend function and factor enums where applicableKristian H. Kristensen2016-11-291-38/+36
| | | | | Signed-off-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/genxml: Use enum 3D_Vertex_Component_Control where applicableKristian H. Kristensen2016-11-291-4/+4
| | | | | Signed-off-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/genxml: Use enum 3D_Stencil_Operation where applicableKristian H. Kristensen2016-11-291-24/+17
| | | | | Signed-off-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/genxml: Use enum SURFACE_FORMAT where applicableKristian H. Kristensen2016-11-291-2/+2
| | | | | Signed-off-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/genxml: Use enum 3D_Prim_Topo_Type where applicableKristian H. Kristensen2016-11-291-3/+3
| | | | | Signed-off-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/genxml: Remove duplicate COMPAREFUNCTION valuesKristian H. Kristensen2016-11-291-40/+4
| | | | | | | | These values were defined both as an enum and as inline values. Remove the inline values and reference the 3D_Compare_Function enum instead. Signed-off-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/genxml: Move enums above structsKristian H. Kristensen2016-11-291-311/+311
| | | | | | | | | We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* genxml: Add values for Barycentric Interpolation ModeKristian H. Kristensen2016-11-291-1/+8
| | | | | Signed-off-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/genxml: Add SO_WRITE_OFFSET registers for gen7-9Jason Ekstrand2016-11-161-0/+16
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/genxml: Make 3DSTATE_WM more consistent across gensJason Ekstrand2016-11-161-3/+13
| | | | | Reviewed-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* intel/genxml: Make some 3DSTATE_PS fields more consistentJason Ekstrand2016-11-161-3/+3
| | | | | Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* intel/genxml: Make some 3DSTATE_GS fields more consistentJason Ekstrand2016-11-161-4/+4
| | | | | Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* intel/genxml: Make some VS/GS fields consistent across gensJason Ekstrand2016-11-161-3/+3
| | | | | | | We use the names from gen8+ Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* intel: genxml: add SAMPLER_BORDER_COLOR_STATE structuresLionel Landwerlin2016-10-181-0/+22
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/genxml: Make some PIPE_CONTROL fields booleansJason Ekstrand2016-10-151-5/+2
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml; Make "Use Global GTT a booleanJason Ekstrand2016-10-151-9/+6
| | | | | | | | We also remove the redundant zero defaults since everything without an explicit default gets zeroed automatically. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml; Make "Tiled Surface" a booleanJason Ekstrand2016-10-151-1/+1
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: Make "SO Buffer Enable" fields booleanJason Ekstrand2016-10-151-4/+4
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: Make "Stencil Buffer Enable" a booleanJason Ekstrand2016-10-151-1/+1
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: Make a couple of STREAMOUT fields booleansJason Ekstrand2016-10-151-2/+2
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: Make "Include Vertex Handles" and "Include Primitive ID" booleansJason Ekstrand2016-10-151-3/+3
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: Make "Vector Mask Enable" a booleanJason Ekstrand2016-10-151-3/+3
| | | | | | | We also get rid of the "(VME)" a few places Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: Make "Single Program Flow" a booleanJason Ekstrand2016-10-151-4/+4
| | | | | | | We also get rid of the "(SPF)" a few places. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: Add a uint MOCS field to 3DSTATE_STENCIL_BUFFERJason Ekstrand2016-10-141-0/+1
| | | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Keep the value name 'Alternate' uniform across gen75.xmlAnuj Phogat2016-10-041-3/+3
| | | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/genxml: Fix typo in gen75.xmlAnuj Phogat2016-10-041-1/+1
| | | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv/cmd_buffer: Set the L3 atomic disable mask bit in CHICKEN3 on HSWJason Ekstrand2016-09-141-0/+1
| | | | | | | | | | | Without this bit set, the value in "L3 Atomic Disable" won't get applied by the hardware so we won't properly get L3 atomic caching. Fixes dEQP-VK.spirv_assembly.instruction.compute.opatomic.compex and 198 of the dEQP-VK.image.atomic_operations.* tests on HSW Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* genxml: Add a uint MOCS field to VERTEX_BUFFER_STATEJason Ekstrand2016-08-191-0/+1
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Make a couple of VERTEX_BUFFER_STATE fields booleanJason Ekstrand2016-08-191-2/+2
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Make VERTEX_ELEMENT_STATE::Valid a boolJason Ekstrand2016-08-191-1/+1
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Add a uint MOCS field to DEPTH_BUFFER packetsJason Ekstrand2016-08-191-0/+2
| | | | | | | This is easier than dealing with structs all the time Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Make 3DSTATE_SF more consistent between gen7 and gen8+Jason Ekstrand2016-08-081-2/+5
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Add APIMODE_D3D missing enum values and improve consistency.Kenneth Graunke2016-07-201-0/+1
| | | | | | Cc: "12.0" <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* genxml: Make X/Y Offset field of SURFACE_STATE a uintJason Ekstrand2016-07-151-2/+2
| | | | | | | | | | | THe offset type has special implications that it's intended to be some form of aligned memory address. These assumptions allow it to handle the case where there is some alignment requirement on the offset and the bottom bits are used for other things. However, the offsets in the surface state field are really just unsigned integers. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* genxml: Make gen6-7 blending look more like gen8Jason Ekstrand2016-07-151-1/+7
| | | | | | | | | | This renames BLEND_STATE to BLEND_STATE_ENTRY and adds an new struct BLEND_STATE which is just an array of 8 BLEND_STATE_ENTRYs. This will make it much easier to write gen-agnostic blend handling code. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: "12.0" <[email protected]>
* genxml: Make ScratchSpaceBasePointer an address instead of an offsetJason Ekstrand2016-06-221-6/+6
| | | | | | | | While we're here, we also fixup MEDIA_VFE_STATE and rename the field in 3DSTATE_VS on gen6-7.5 to be consistent with the others. Signed-off-by: Jason Ekstrand <[email protected]> Cc: "12.0" <[email protected]>
* genxml: Put append counter fields before MCS in RENDER_SURFACE_STATE on gen7Jason Ekstrand2016-06-221-2/+2
| | | | | | | | | | The pack header generation scripts can't handle the case where you have two addresses in the same dword; they just take whatever is the last one. This meant that the MCS address wasn't properly getting handled. Since we don't care about append counters, we can just re-arrange the XML for now. Reviewed-by: Chad Versace <[email protected]> Cc: "12.0" <[email protected]>
* genxml/gen6,7,75: s/BackFace/BackfaceJason Ekstrand2016-06-031-2/+2
| | | | | | | | This is more consistent with gen8+ Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: "12.0" <[email protected]>
* genxml: Make PIPE_CONTROL::CommandStreamerStallEnable a booleanJason Ekstrand2016-05-271-1/+1
| | | | | | | This has been declared as a uint since SNB but it's only one bit. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* genxml/hsw: Add L3 cache control registersJordan Justen2016-05-171-0/+8
| | | | | | | | These were added to the i965 driver in 5912da45a69923afa1b7f2eb5bb371d848813c41. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* genxml: Fix the name of a 3DSTATE_SF/SBE field on gen6-7.5Jason Ekstrand2016-04-091-1/+1
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* genxml: Add L3 Cache Control register definitionsJordan Justen2016-03-241-0/+26
| | | | | | Based on intel_reg.h (5912da45a69923afa1b7f2eb5bb371d848813c41) Signed-off-by: Jordan Justen <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-27 06:33:05 +0000