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path: root/src/intel/genxml/gen12.xml
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* intel/genxml: Add 3DSTATE_CONSTANT_ALL packet.Rafael Antognolli2019-12-041-0/+25
* intel/genxml: Add gen12 tile cache flush bitJordan Justen2019-10-301-0/+1
* genxml/gen12: Add Stencil Buffer Resolve Enable bitSagar Ghuge2019-10-291-0/+1
* genxml: Add 3DSTATE_SO_BUFFER_INDEX_* instructionsPlamena Manolova2019-10-291-0/+47
* genxml: Change 3DSTATE_DEPTH_BOUNDS bias.Plamena Manolova2019-10-291-1/+1
* intel: Fix and use HIZ_CCS write through modeNanley Chery2019-10-281-0/+1
* intel: Use 3DSTATE_DEPTH_BUFFER::ControlSurfaceEnableNanley Chery2019-10-281-0/+1
* intel: Use RENDER_SURFACE_STATE::DepthStencilResourceNanley Chery2019-10-281-0/+1
* intel/blorp/gen12: Set FWCC when storing the clear color.Rafael Antognolli2019-10-281-0/+1
* genxml: Add 3DSTATE_DEPTH_BOUNDS instruction.Plamena Manolova2019-10-281-0/+13
* genxml/gen12: Add AUX MAP register definitionsJordan Justen2019-10-281-0/+8
* intel/genxml: add RPSTAT register for core frequencyLionel Landwerlin2019-10-231-0/+5
* intel/genxml: Remove W-tiling on gen12Jason Ekstrand2019-10-171-1/+0
* intel/genxml,isl: Add gen12 stencil buffer changesJordan Justen2019-10-171-5/+30
* intel/genxml,isl: Add gen12 depth buffer changesJordan Justen2019-10-171-9/+13
* intel/genxml,isl: Add gen12 render surface state changesJordan Justen2019-10-171-10/+9
* genxml/gen11+: Add COMMON_SLICE_CHICKEN4 registerAnuj Phogat2019-09-111-0/+5
* anv,iris: L3ALLOC register replaces L3CNTLREG for gen12Jordan Justen2019-09-061-4/+3
* intel/genxml: Add gen12.xml as a copy of gen11.xmlJordan Justen2019-08-281-0/+7171
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