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path: root/src/intel/genxml/gen11.xml
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* intel/genxml: add PIPE_CONTROL command cache invalidate bitLionel Landwerlin2020-05-201-0/+1
* genxml: fix invalid end value for video fieldsLionel Landwerlin2020-05-091-1/+1
* genxml: run sorting scriptLionel Landwerlin2020-05-091-8/+8
* intel/genxml: Drop SLMEnable from L3CNTLREG on Gen11Jason Ekstrand2020-01-301-1/+0
* intel/genxml: Make SO_DECL::"Hole Flag" a BooleanJason Ekstrand2020-01-271-1/+1
* genxml: add new Gen11+ PIPE_CONTROL fieldLionel Landwerlin2020-01-161-0/+1
* genxml: Remove a non-existant HW bitJason Ekstrand2020-01-091-1/+0
* intel/genxml: Add a partial TCCNTLREG definitionKenneth Graunke2019-12-101-0/+7
* intel/genxml: add RPSTAT register for core frequencyLionel Landwerlin2019-10-231-0/+5
* intel/genxml: add generic perf counters registersLionel Landwerlin2019-10-231-0/+18
* genxml/gen11+: Add COMMON_SLICE_CHICKEN4 registerAnuj Phogat2019-09-111-0/+5
* intel/genxml: Run sort_xml.sh to tidy gen9.xml and gen11.xmlJordan Justen2019-08-281-21/+19
* intel/genxml/gen11: Add spaces in EnableUnormPathInColorPipeJordan Justen2019-08-281-1/+1
* isl: Enable Unorm Path in Color PipeKenneth Graunke2019-08-151-0/+1
* intel/genxml: Update 3D_MODE and add SLICE_HASH_TABLE.Rafael Antognolli2019-08-121-1/+33
* intel/genxml: correct bit fields in CACHE_MODE_0 reg for gen11Dongwon Kim2019-07-081-16/+14
* intel/genxml: Update MI_ATOMIC genxml definition.Rafael Antognolli2019-04-291-5/+39
* iris: implement WaEnableStateCacheRedirectToCSLionel Landwerlin2019-04-181-0/+5
* genxml: sort xml files using new scriptLionel Landwerlin2019-04-091-3713/+3701
* intel/genxml: Media instructions and structures for gen11Toni Lönnberg2019-03-281-24/+3450
* anv/icl: Add WA_2204188704 to disable pixel shader panic dispatchAnuj Phogat2019-03-191-0/+5
* genxml: add missing field values for 3DSTATE_SFJuan A. Suarez Romero2019-02-221-1/+4
* genxml: Add SO_PRIM_STORAGE_NEEDED and SO_NUM_PRIMS_WRITTENJason Ekstrand2019-01-221-0/+32
* intel/genxml: add missing MI_PREDICATE compare operationsLionel Landwerlin2019-01-191-0/+2
* intel/genxml: Add register for object preemption.Rafael Antognolli2018-12-141-0/+8
* genxml: Consistently use a numeric "MOCS" fieldKenneth Graunke2018-12-141-32/+21
* anv/icl: Set use full ways in L3CNTLREGAnuj Phogat2018-11-261-0/+1
* intel/genxml: Add engine definition to render engine instructions (gen11)Toni Lönnberg2018-11-131-116/+116
* anv/icl: Set Error Detection Behavior Control Bit in L3CNTLREGAnuj Phogat2018-11-011-0/+1
* anv/icl: Set Enabled Texel Offset Precision Fix bitAnuj Phogat2018-09-211-0/+5
* anv/icl: Allow headerless sampler messages for pre-emptable contextsAnuj Phogat2018-08-211-0/+5
* intel/genxml: Add bitmasks for CS_DEBUG_MODE2/INSTPM.Rafael Antognolli2018-06-181-0/+4
* intel/genxml: Fix some more fake booleans in genxml.Kenneth Graunke2018-05-071-5/+5
* intel/genxml: Add Clear Color struct to gen10+.Rafael Antognolli2018-04-051-0/+10
* intel/genxml: Use a single field for clear color address on gen10.Rafael Antognolli2018-04-051-4/+3
* intel: genxml: decode variable length MI_LRILionel Landwerlin2018-04-031-0/+4
* intel: genxml: add preemption control instructionsLionel Landwerlin2018-04-031-0/+7
* intel/genxml: Add SAMPLER_INSTDONE register.Rafael Antognolli2018-03-261-0/+23
* intel/genxml: Add ROW_INSTDONE register.Rafael Antognolli2018-03-261-0/+18
* intel/genxml: Add SC_INSTDONE register.Rafael Antognolli2018-03-261-0/+27
* intel: genxml: add INSTPM/CS_DEBUG_MODE2 registersLionel Landwerlin2018-03-201-0/+6
* intel: Drop SURFACE_FORMAT enum from genxml.Kenneth Graunke2018-03-051-227/+2
* intel/genxml/icl: Add gen11.xmlAnuj Phogat2018-02-151-0/+3765
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