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* intel/genxml: Make SO_DECL::"Hole Flag" a BooleanJason Ekstrand2020-01-271-1/+1
| | | | | Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3520>
* genxml: Remove a non-existant HW bitJason Ekstrand2020-01-091-1/+0
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* intel/genxml: add RPSTAT register for core frequencyLionel Landwerlin2019-10-231-0/+5
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: add generic perf counters registersLionel Landwerlin2019-10-231-0/+18
| | | | | | | | | | We have 2 of those we can configure to source programmable events. Those are not part of the OA reports. Configuration happens in i915 through the metric set selected by the application. On the Mesa side we'll just sample those and do a diff. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: Update MI_ATOMIC genxml definition.Rafael Antognolli2019-04-291-5/+39
| | | | | | | Change some of the single bit fields to booleans, and add an enum with the definition of the ATOMIC_OPCODE. Reviewed-by: Lionel Landwerlin <[email protected]>
* genxml: sort xml files using new scriptLionel Landwerlin2019-04-091-3633/+3625
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* intel/genxml: Media instructions and structures for gen10Toni Lönnberg2019-03-281-24/+3284
| | | | | | | | | | | v2: Lionel Landwerlin <[email protected]> - fix missing type - fix *_FQM_*/*_QM_* commands - shorten some media structs using groups - factor out memory attributes - switch MI_FLUSH_DW fields to bool Reviewed-by: Lionel Landwerlin <[email protected]>
* genxml: add missing field values for 3DSTATE_SFJuan A. Suarez Romero2019-02-221-1/+4
| | | | | | | | | Fill out "Vertex Sub Pixel Precision Select" possible values. CC: 18.3 19.0 <[email protected]> Signed-off-by: Juan A. Suarez Romero <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* genxml: Add SO_PRIM_STORAGE_NEEDED and SO_NUM_PRIMS_WRITTENJason Ekstrand2019-01-221-0/+32
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: add missing MI_PREDICATE compare operationsLionel Landwerlin2019-01-191-0/+2
| | | | | | | | Doesn't save us a great deal of lines but at least they get decoded in aubinators. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: Add register for object preemption.Rafael Antognolli2018-12-141-0/+8
| | | | | Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Consistently use a numeric "MOCS" fieldKenneth Graunke2018-12-141-32/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When we first started using genxml, we decided to represent MOCS as an actual structure, and pack values. However, in many places, it was more convenient to use a numeric value rather than treating it as a struct, so we added secondary setters in a bunch of places as well. We were not entirely consistent, either. Some places only had one. Gen6 had both kinds of setters for STATE_BASE_ADDRESS, but newer gens only had the struct-based setters. The names were sometimes "Constant Buffer Object Control State" instead of "Memory", making it harder to find. Many had prefixes like "Vertex Buffer MOCS"...in a vertex buffer packet...which is a bit redundant. On modern hardware, MOCS is simply an index into a table, but we were still carrying around the structure with an "Index to MOCS Table" field, in addition to the direct numeric setters. This is clunky - we really just want a number on new hardware. This patch eliminates the struct-based setters, and makes the numeric setters be consistently called "MOCS". We leave the struct definition around on Gen7-8 for reference purposes, but it is unused. v2: Drop bonus "Depth Buffer MOCS" fields on Gen7.5 and Gen9 Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* intel/genxml: Add engine definition to render engine instructions (gen10)Toni Lönnberg2018-11-131-113/+113
| | | | | | | | | | | | | | Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine definition to MI_TOPOLOGY_FILTER. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: turn SLM Enable bit into booleanLionel Landwerlin2018-09-071-1/+1
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/genxml: Add bitmasks for CS_DEBUG_MODE2/INSTPM.Rafael Antognolli2018-06-181-0/+4
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Fix some more fake booleans in genxml.Kenneth Graunke2018-05-071-2/+2
| | | | | | | | | None of these are actually booleans. Tile Parameter is a tiling mode enum. Display pipes take plane numbers. Predicate Enable has some operations (and the default value of 6 was particular bogus). Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/genxml: Add Clear Color struct to gen10+.Rafael Antognolli2018-04-051-0/+8
| | | | | | | v5: Split genxml changes into its own commit (Jason). Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/genxml: Use a single field for clear color address on gen10.Rafael Antognolli2018-04-051-4/+3
| | | | | | | | | | | | | | | | | | | | genxml does not support having two address fields with different names but same position in the state struct. Both "Clear Color Address" and "Clear Depth Address Low" mean the same thing, only for different surface types. To workaround this genxml limitation, rename "Clear Color Address" to "Clear Value Address" and use it for both color and depth. Do the same for the high bits. TODO: add support for multiple addresses at the same position in the xml. v2: Combine high and low order bits into a single address field. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* intel: genxml: decode variable length MI_LRILionel Landwerlin2018-04-031-0/+4
| | | | | | | | | | | | | | | MI_LOAD_REGISTER_IMM can load multiple (register, value) tuples in one command. In our drivers we only use one tuple at a time, but the kernel might load more than one at a time. Instead of making all the tuple part of a group, we leave out the first tuple (the one we use in the generated packing structures). This is particularly useful for looking at error stats generated by the kernel. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* intel: genxml: add preemption control instructionsLionel Landwerlin2018-04-031-0/+7
| | | | | | | Helpful to debug kernel workaround batchbuffers. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* intel/genxml: Add SAMPLER_INSTDONE register.Rafael Antognolli2018-03-261-0/+23
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Add ROW_INSTDONE register.Rafael Antognolli2018-03-261-0/+18
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Add SC_INSTDONE register.Rafael Antognolli2018-03-261-0/+27
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* intel: genxml: add INSTPM/CS_DEBUG_MODE2 registersLionel Landwerlin2018-03-201-0/+6
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Drop SURFACE_FORMAT enum from genxml.Kenneth Graunke2018-03-051-227/+2
| | | | | | | | | | | We want people to be using ISL_FORMAT_*, rather than the genxml format enumerations. This patch drops 10 separate copies, and drops a bunch of ugly casting. Reviewed-by: Jordan Justen <[email protected]> [[email protected]: Minor changes for rebase] Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* genxml: Add missing INSTDONE_1 bits on Gen7.5+.Kenneth Graunke2018-01-091-0/+2
| | | | | | This will make aubinator_error_decode decode them properly. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Add Cache Mode SubSlice Register to gen10.xmlAnuj Phogat2017-11-141-0/+12
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: Fix gen10 BLEND_STATE variable length packingScott D Phillips2017-08-151-2/+2
| | | | | | | | | | | | | | | | BLEND_STATE packing was modified to be variable-length in: 9670124e31 genxml: Make BLEND_STATE command support variable length array. The initial gen10.xml still had the old, fixed-length style definition for BLEND_STATE. So gen10_upload_blend_state would overwrite the packed BLEND_STATE_ENTRYs with its own fixed array of all-zero entries when packing BLEND_STATE. This caused BLEND_STATE upload to not work at all. Fixes: aa416f515a ("i965/genxml: Add gen10.xml") Reviewed-by: Rafael Antognolli <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* intel: genxml: make a couple of enums show up in aubinatorLionel Landwerlin2017-07-021-7/+7
| | | | | | | In particular Shader Channel Select & Texture Address Control Mode. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* intel/genxml: Add Gen10 CACHE_MODE_1 definitionsAnuj Phogat2017-06-221-0/+18
| | | | | | | | | | Few of the fields in this register are changed as compared to gen9.xml. V2: Remove some fields which are not valid anymore. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: Rename StartInstanceLocation to StartingInstanceLocationAnuj Phogat2017-06-221-1/+1
| | | | | | | | This is required because we already have a macro defined with the name StartInstanceLocation. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: Rename IndirectStatePointer to BorderColorPointerAnuj Phogat2017-06-221-1/+1
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: Combine DataDWord{0, 1} fields in to ImmediateData fieldAnuj Phogat2017-06-221-2/+1
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: Add INSTDONE registers in gen10Anuj Phogat2017-06-221-0/+115
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: Add better support for MI_MATH in gen10Anuj Phogat2017-06-221-4/+65
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* i965/genxml: Add gen10.xmlJason Ekstrand2017-06-091-0/+3562
V2(Anuj): Add default value for length of 3DPRIMITIVE command Add values for 'Attribute Active Component Format' Rename few fields to match gen9.xml V3 (Ander Conselvan de Oliveira) Add gen10 alias for MOCS Make 3DSTATE_CONSTANT_BODY on Gen10 use arrays Signed-off-by: Anuj Phogat <[email protected]> Tested-by: Anuj Phogat <[email protected]>
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