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path: root/src/intel/genxml/gen10.xml
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* intel/genxml: add RPSTAT register for core frequencyLionel Landwerlin2019-10-231-0/+5
* intel/genxml: add generic perf counters registersLionel Landwerlin2019-10-231-0/+18
* intel/genxml: Update MI_ATOMIC genxml definition.Rafael Antognolli2019-04-291-5/+39
* genxml: sort xml files using new scriptLionel Landwerlin2019-04-091-3633/+3625
* intel/genxml: Media instructions and structures for gen10Toni Lönnberg2019-03-281-24/+3284
* genxml: add missing field values for 3DSTATE_SFJuan A. Suarez Romero2019-02-221-1/+4
* genxml: Add SO_PRIM_STORAGE_NEEDED and SO_NUM_PRIMS_WRITTENJason Ekstrand2019-01-221-0/+32
* intel/genxml: add missing MI_PREDICATE compare operationsLionel Landwerlin2019-01-191-0/+2
* intel/genxml: Add register for object preemption.Rafael Antognolli2018-12-141-0/+8
* genxml: Consistently use a numeric "MOCS" fieldKenneth Graunke2018-12-141-32/+21
* intel/genxml: Add engine definition to render engine instructions (gen10)Toni Lönnberg2018-11-131-113/+113
* intel/genxml: turn SLM Enable bit into booleanLionel Landwerlin2018-09-071-1/+1
* intel/genxml: Add bitmasks for CS_DEBUG_MODE2/INSTPM.Rafael Antognolli2018-06-181-0/+4
* intel/genxml: Fix some more fake booleans in genxml.Kenneth Graunke2018-05-071-2/+2
* intel/genxml: Add Clear Color struct to gen10+.Rafael Antognolli2018-04-051-0/+8
* intel/genxml: Use a single field for clear color address on gen10.Rafael Antognolli2018-04-051-4/+3
* intel: genxml: decode variable length MI_LRILionel Landwerlin2018-04-031-0/+4
* intel: genxml: add preemption control instructionsLionel Landwerlin2018-04-031-0/+7
* intel/genxml: Add SAMPLER_INSTDONE register.Rafael Antognolli2018-03-261-0/+23
* intel/genxml: Add ROW_INSTDONE register.Rafael Antognolli2018-03-261-0/+18
* intel/genxml: Add SC_INSTDONE register.Rafael Antognolli2018-03-261-0/+27
* intel: genxml: add INSTPM/CS_DEBUG_MODE2 registersLionel Landwerlin2018-03-201-0/+6
* intel: Drop SURFACE_FORMAT enum from genxml.Kenneth Graunke2018-03-051-227/+2
* genxml: Add missing INSTDONE_1 bits on Gen7.5+.Kenneth Graunke2018-01-091-0/+2
* intel/genxml: Add Cache Mode SubSlice Register to gen10.xmlAnuj Phogat2017-11-141-0/+12
* intel/genxml: Fix gen10 BLEND_STATE variable length packingScott D Phillips2017-08-151-2/+2
* intel: genxml: make a couple of enums show up in aubinatorLionel Landwerlin2017-07-021-7/+7
* intel/genxml: Add Gen10 CACHE_MODE_1 definitionsAnuj Phogat2017-06-221-0/+18
* intel/genxml: Rename StartInstanceLocation to StartingInstanceLocationAnuj Phogat2017-06-221-1/+1
* intel/genxml: Rename IndirectStatePointer to BorderColorPointerAnuj Phogat2017-06-221-1/+1
* intel/genxml: Combine DataDWord{0, 1} fields in to ImmediateData fieldAnuj Phogat2017-06-221-2/+1
* intel/genxml: Add INSTDONE registers in gen10Anuj Phogat2017-06-221-0/+115
* intel/genxml: Add better support for MI_MATH in gen10Anuj Phogat2017-06-221-4/+65
* i965/genxml: Add gen10.xmlJason Ekstrand2017-06-091-0/+3562
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