aboutsummaryrefslogtreecommitdiffstats
path: root/src/intel/dev
Commit message (Collapse)AuthorAgeFilesLines
* intel: limit shader geometry on BDW GT1Ross Zwisler2019-12-201-1/+2
| | | | | | | | | | | | | | | | | | | | | Similar to the SKL GT1 fix introduced here: https://gitlab.freedesktop.org/asimiklit/mesa/commit/b1ba7ffdbd54fdb5da18d086c7b7a830e06a1cff we need to limit the .urb.max_entries[MESA_SHADER_GEOMETRY] on BDW GT1 to address failures in these two tests: dEQP-GLES31.functional.geometry_shading.layered.render_with_default_layer_3d dEQP-GLES31.functional.geometry_shading.layered.render_with_default_layer_2d_array The value 690 was found via bisection. 691 is the actual max on the hardware I'm using, but 690 seemed like a nice round number. Signed-off-by: Ross Zwisler <[email protected]> Signed-off-by: Lionel Landwerlin <[email protected]> Acked-by: Lionel Landwerlin <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3173> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3173>
* intel: Add pci-ids for Jasper LakeAnuj Phogat2019-12-091-0/+1
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel: Add device info for 1x4x6 Jasper LakeAnuj Phogat2019-12-091-4/+21
| | | | | | | | Also removing the FIXME comments after matching the numbers with updated documentation. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/dev: flag the Elkhart Lake platformLionel Landwerlin2019-11-152-0/+5
| | | | | | | We'll use this for performance metrics which are different from ICL. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/dev: set default num_eu_per_subslice on gen12Lionel Landwerlin2019-10-301-1/+2
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: 8125d7960b ("intel/dev: Add preliminary device info for Tigerlake") Acked-by: Jason Ekstrand <[email protected]>
* intel/dev: Add preliminary device info for TigerlakeJordan Justen2019-10-301-0/+49
| | | | | | | | | | | Reworks: * adjust 64-bit support, hiz (Jason Ekstrand) * sim-id (Lionel Landwerlin) * adjust threads, urb size (Rafael Antognolli) * adjust urb size (Kenneth Graunke) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* loader: default to iris for all future PCI IDsEric Engestrom2019-10-282-0/+3
| | | | | | | | | | The existing "fallback" code didn't actually do anything, so this removes it, and instead we just always fallback to `iris` for future PCI IDs. Suggested-by: Kenneth Graunke <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/dev: store whether the device uses an aux map tables on devinfoLionel Landwerlin2019-10-281-0/+1
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Add INTEL_DEBUG=nofc for disabling fast clearsCaio Marcelo de Oliveira Filho2019-10-092-0/+2
| | | | Reviewed-by: Rafael Antognolli <[email protected]>
* intel: fix subslice computation from topology dataLionel Landwerlin2019-10-051-1/+1
| | | | | | | | | | | | We're missing the offset of the slice in the subslice mask... This worked for most platforms that don't have first slice fused off because we would reread the same mask from slice0 again and again... Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: c1900f5b0f ("intel: devinfo: add helper functions to fill fusing masks values") Gitlab: https://gitlab.freedesktop.org/mesa/mesa/issues/1869 Reviewed-by: Mark Janes <[email protected]>
* intel: fix topology queryLionel Landwerlin2019-10-021-0/+3
| | | | | | | | | | | | | | | | | i915 will report ENODEV on generations prior to Haswell because there is no point in reporting values on those. This is prior any fusing could happen on parts with identical PCI ids. This query call was previously only triggered on generations that support performance queries, which happens to match generation for which i915 reports topology, but the commit pointed below started using it on all generations. Signed-off-by: Lionel Landwerlin <[email protected]> Gitlab: https://gitlab.freedesktop.org/mesa/mesa/issues/1860 Cc: <[email protected]> Fixes: 96e1c945f2 ("i965: Move device info initialization to common code") Reviewed-by: Mark Janes <[email protected]>
* intel: Get information about pixel pipes subslices.Rafael Antognolli2019-08-122-1/+25
| | | | v2: Use 1 instead of 1UL (Ken).
* intel/device: make internal functions privateMark Janes2019-08-012-84/+68
| | | | | | | | | | | | | The device info initializer makes several fuctions internal: - handling of device override - updating topology from kernel information The implementation file is slightly reordered due to the renamed functions being static. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/device: rename gen_get_device_infoMark Janes2019-08-013-8/+10
| | | | | | | | | | | | | | | | | | Rename the original device info initialization routine so callers don't mistakenly call the wrong one: gen_get_device_info_from_fd: Queries kernel for full device info, including topology details. gen_get_device_info_from_pci_id: Partially initializes device info based on PCI ID lookup, when the kernel is not available. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* i965: Move device info initialization to common codeMark Janes2019-08-012-0/+137
| | | | | | | | | | | With perf queries, initializing the device info is much more complex than just getting a PCI ID and calling gen_get_device_info. This commit adds a new gen_get_device_info_from_fd helper in common code which does all of the requisite kernel queries to get device info including all of the topology information. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel: replace large stack buffer with heap allocationEric Engestrom2019-07-292-27/+32
| | | | | | | | | For now, this keeps the "100 bytes" allocation; we can try to figure out the correct size as a follow up. Suggested-by: Lionel Landwerlin <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel: add disable_ccs_repack to gen_device_infoDongwon Kim2019-07-082-0/+4
| | | | | | | | | | add a new attribute, 'disable_ccs_repack' to gen_device info, which indicates whether repacking of components in certain pixel formats before compression needs to be disabled to keep the compatibility with decompression capability of display controller (gen11+) Signed-off-by: Dongwon Kim <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* iris: Implement INTEL_DEBUG=pc for pipe control logging.Kenneth Graunke2019-06-202-0/+2
| | | | | | | | This prints a log of every PIPE_CONTROL flush we emit, noting which bits were set, and also the reason for the flush. That way we can see which are caused by hardware workarounds, render-to-texture, buffer updates, and so on. It should make it easier to determine whether we're doing too many flushes and why.
* iris: Print binding tables when INTEL_DEBUG=btCaio Marcelo de Oliveira Filho2019-06-032-0/+2
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/compiler: Implement TCS 8_PATCH mode and INTEL_DEBUG=tcs8Kenneth Graunke2019-05-142-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Our tessellation control shaders can be dispatched in several modes. - SINGLE_PATCH (Gen7+) processes a single patch per thread, with each channel corresponding to a different patch vertex. PATCHLIST_N will launch (N / 8) threads. If N is less than 8, some channels will be disabled, leaving some untapped hardware capabilities. Conditionals based on gl_InvocationID are non-uniform, which means that they'll often have to execute both paths. However, if there are fewer than 8 vertices, all invocations will happen within a single thread, so barriers can become no-ops, which is nice. We also burn a maximum of 4 registers for ICP handles, so we can compile without regard for the value of N. It also works in all cases. - DUAL_PATCH mode processes up to two patches at a time, where the first four channels come from patch 1, and the second group of four come from patch 2. This tries to provide better EU utilization for small patches (N <= 4). It cannot be used in all cases. - 8_PATCH mode processes 8 patches at a time, with a thread launched per vertex in the patch. Each channel corresponds to the same vertex, but in each of the 8 patches. This utilizes all channels even for small patches. It also makes conditions on gl_InvocationID uniform, leading to proper jumps. Barriers, unfortunately, become real. Worse, for PATCHLIST_N, the thread payload burns N registers for ICP handles. This can burn up to 32 registers, or 1/4 of our register file, for URB handles. For Vulkan (and DX), we know the number of vertices at compile time, so we can limit the amount of waste. In GL, the patch dimension is dynamic state, so we either would have to waste all 32 (not reasonable) or guess (badly) and recompile. This is unfortunate. Because we can only spawn 16 thread instances, we can only use this mode for PATCHLIST_16 and smaller. The rest must use SINGLE_PATCH. This patch implements the new 8_PATCH TCS mode, but leaves us using SINGLE_PATCH by default. A new INTEL_DEBUG=tcs8 flag will switch to using 8_PATCH mode for testing and benchmarking purposes. We may want to consider using 8_PATCH mode in Vulkan in some cases. The data I've seen shows that 8_PATCH mode can be more efficient in some cases, but SINGLE_PATCH mode (the one we use today) is faster in other cases. Ultimately, the TES matters much more than the TCS for performance, so the decision may not matter much. Reviewed-by: Jason Ekstrand <[email protected]>
* intel: drop misleading driver name from gen_get_device_info()Mike Blumenkrantz2019-05-111-1/+1
|
* intel: workaround VS fixed function issue on Gen9 GT1 partsLionel Landwerlin2019-04-231-0/+12
| | | | | | | | | | | | The issue is noticeable in the dEQP-GLES31.functional.geometry_shading.layered.render_with_default_layer_3d test where a triangle goes missing when we use the maximum number of URB entries as specified by the documentation. Signed-off-by: Lionel Landwerlin <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107505 Reviewed-by: Kristian H. Kristensen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* intel/devinfo: add basic sanity tests on device databaseLionel Landwerlin2019-04-192-0/+45
| | | | | | | | | v2: #undef NDEBUG (Eric) Use inc_include & inc_src (Eric) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Anuj Phogat [email protected]
* intel/devinfo: fix missing num_thread_per_eu on ICLLionel Landwerlin2019-04-191-6/+2
| | | | | | | | | | | There was an assumption that num_thread_per_eu would be set in the Gen8 features. Since this is mostly the same of all gen8->11 (except GEN9_LP that overwrites it) let's just factor it out. Signed-off-by: Lionel Landwerlin <[email protected]> Cc: [email protected] Acked-by: Eric Engestrom <[email protected]> Reviewed-by: Anuj Phogat [email protected]
* i965: move brw_timebase_scale to device infoLionel Landwerlin2019-04-171-0/+7
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Mark Janes <[email protected]>
* i965: store device revision in gen_device_infoLionel Landwerlin2019-04-171-0/+1
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/common: move gen_debug to intel/devMark Janes2019-04-103-0/+246
| | | | | | | | | libintel_common depends on libintel_compiler, but it contains debug functionality that is needed by libintel_compiler. Break the circular dependency by moving gen_debug files to libintel_dev. Suggested-by: Kenneth Graunke <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Add support for Comet LakeAnuj Phogat2019-04-011-0/+1
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* intel: Add Elkhart Lake device infoAnuj Phogat2019-03-271-0/+60
| | | | | | | | V2: Fix L3 bank count (Vivek) Fix simulator_id and num_eu_per_subslice (Lionel) Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel: fix urb size for CFL GT1Lionel Landwerlin2019-02-221-0/+1
| | | | | | | | Same 192Kb amount as SKL/KBL GT1 applies. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Fixes: de7ed0ba5522 ("i965/CFL: Add PCI Ids for Coffee Lake.")
* drm-uapi: use local files, not system libdrmEric Engestrom2019-02-142-2/+2
| | | | | | | | | There was an issue recently caused by the system header being included by mistake, so let's just get rid of this include path and always explicitly #include "drm-uapi/FOO.h" Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* intel: Introducing Whiskey Lake platformRodrigo Vivi2018-10-111-0/+1
| | | | | | | | | | | | | | | | | | | Whiskey Lake uses the same gen graphics as Coffe Lake, including some ids that were previously marked as reserved on Coffe Lake, but that now are moved to WHL page. This follows the ids and approach used on kernel's commit b9be78531d27 ("drm/i915/whl: Introducing Whiskey Lake platform") and commit c1c8f6fa731b ("drm/i915: Redefine some Whiskey Lake SKUs") v2: Lionel noticed that GT{1,2,3} on kernel wasn't following spec when looking to number of EUs, so kernel has been updated. Cc: Lionel Landwerlin <[email protected]> Cc: José Roberto de Souza <[email protected]> Cc: Anuj Phogat <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/icl: Fix URB size for different SKUsAnuj Phogat2018-09-211-14/+29
| | | | | | | Different ICL SKUs have different URB sizes. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Introducing Amber Lake platformRodrigo Vivi2018-08-311-0/+1
| | | | | | | | | | | | | | | Amber Lake uses the same gen graphics as Kaby Lake, including a id that were previously marked as reserved on Kaby Lake, but that now is moved to AML page. This follows the ids and approach used on kernel's commit e364672477a1 ("drm/i915/aml: Introducing Amber Lake platform") Reported-by: Timo Aaltonen <[email protected]> Cc: José Roberto de Souza <[email protected]> Cc: Anuj Phogat <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel: devinfo: add simulator idLionel Landwerlin2018-07-052-4/+48
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* i965/glk: Add l3 banks count for 2x6 configurationAnuj Phogat2018-05-211-1/+1
| | | | | | | | | | | | 2x6 configuration with pci-id 0x3185 has same number of banks (2) as 3x6 configuration (pci-id 0x3184). Reported-by: Clayton Craft <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Tested-by: Clayton Craft <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Fixes: eb23be1d97da "i965: Add and initialize l3_banks field for gen7+" Cc: Francisco Jerez <[email protected]>
* intel: devinfo: silence coverity warningLionel Landwerlin2018-05-091-0/+1
| | | | | | | | It's just not possible to have a device with no subslices. CID: 1433511 Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel: devinfo: fix assertion on devices with odd number of EUsLionel Landwerlin2018-05-081-5/+1
| | | | | | | | | | | | I forgot to change the assert in the second helper function in a previous change. This hit the assert() on a Broadwell platform with 1 slice, 3 subslices but all EUs disabled in subslice 1 & 2. Fixes: c1900f5b0fb ("intel: devinfo: add helper functions to fill fusing masks values") Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/dev: Assert the number of slices is not zeroTopi Pohjolainen2018-04-111-1/+1
| | | | | | | Fixes: c1900f5b intel: devinfo: add helper functions to fill... CID: 1433511 Reviewed-by: Lionel Landwerlin <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965: perf: query topologyLionel Landwerlin2018-03-221-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the introduction of asymmetric slices in CNL, we cannot rely on the previous SUBSLICE_MASK getparam to tell userspace what subslices are available. We introduce a new uAPI in the kernel driver to report exactly what part of the GPU are fused and require this to be available on Gen10+. Prior generations can continue to rely on GETPARAM on older kernels. This patch is quite a lot of code because we have to support lots of different kernel versions, ranging from not providing any information (for Haswell on 4.13 through 4.17), to being able to query through GETPARAM (for gen8/9 on 4.13 through 4.17), to finally requiring 4.17 for Gen10+. This change stores topology information in a unified way on brw_context.topology from the various kernel APIs. And then generates the appropriate values for the equations from that unified topology. v2: Move slice/subslice masks fields to gen_device_info (Rafael) v3: Add a gen_device_info_subslice_available() helper (Lionel) Signed-off-by: Lionel Landwerlin <[email protected]> Acked-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: devinfo: add helper functions to fill fusing masks valuesLionel Landwerlin2018-03-222-1/+140
| | | | | | | | | | | | | | | | | | | | | | There are a couple of ways we can get the fusing information from the kernel : - Through DRM_I915_GETPARAM with the SLICE_MASK/SUBSLICE_MASK parameters - Through the new DRM_IOCTL_I915_QUERY by requesting the DRM_I915_QUERY_TOPOLOGY_INFO The second method is more accurate and also gives us the EUs fusing masks. It's also a requirement for CNL as this platform has asymetric subslices and the first method SUBSLICE_MASK value is assumed uniform across slices. v2: Change gen_device_info_update_from_masks() to generate topology and call into gen_device_info_update_from_topology (Lionel/Ken) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: devinfo: meson: include drm uapiLionel Landwerlin2018-03-221-1/+1
| | | | | | | Already available with the autotools build. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: devinfo: store slice/subslice/eu masksLionel Landwerlin2018-03-222-1/+91
| | | | | | | | | | | We want to store values coming from the kernel but as a first step, we can generate mask values out the numbers already stored in the gen_device_info masks. v2: Add a helper to set EU masks (Lionel/Ken) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: devinfo: store number of EUs per subsliceLionel Landwerlin2018-03-222-2/+38
| | | | | | | | | | | This will be reused to store values reported by the kernel. The main use case will be for use as the input values of the metric sets equations for the INTEL_performance_queries extension. By storing this information in the gen_device_info we make this non GL specific so this can be reused by Vulkan if we ever have an equivalent extension. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/common/icl: Disable hiz surface samplingAnuj Phogat2018-03-221-0/+1
| | | | | | | | On gen11+ AUX_HIZ is not a supported value for surfaces being sampled by the 3D sampler. Reviewed-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Add cfl to gen_device_name_to_pci_device_id()Matt Turner2018-03-161-0/+1
| | | | Reviewed-by: Rafael Antognolli <[email protected]>
* intel: Split gen_device_info out into libintel_devJordan Justen2018-03-053-0/+1148
Split out the device info so isl doesn't depend on intel/common. Now it will depend on the new intel/dev device info lib. This will allow the decoder in intel/common to use isl, allowing us to apply Ken's patch that removes the genxml duplication of surface formats. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-11 19:06:53 +0000