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* i965: Drop support for the legacy SNORM -> Float equation.Kenneth Graunke2018-01-027-41/+13
* i965: Combine {VS,FS}_OPCODE_GET_BUFFER_SIZE opcodes.Kenneth Graunke2017-12-308-19/+14
* Revert "i965/fs: Use align1 mode on ternary instructions on Gen10+"Anuj Phogat2017-12-221-8/+4
* intel/fs: Initialize fs_visitor::grf_used on construction.Francisco Jerez2017-12-211-0/+1
* intel/fs/bank_conflicts: Use posix_memalign() instead of overaligned new to o...Francisco Jerez2017-12-211-6/+16
* intel/compiler/gen10: Disable push constants.Rafael Antognolli2017-12-191-0/+9
* intel/fs/bank_conflicts: Don't touch Gen7 MRF hack registers.Francisco Jerez2017-12-123-7/+19
* i965/fs: Handle !supports_pull_constants and push UBOs properlyJason Ekstrand2017-12-081-1/+1
* i965/fs: Rewrite assign_constant_locationsJason Ekstrand2017-12-081-133/+185
* intel/cfg: Represent divergent control flow paths caused by non-uniform loop ...Francisco Jerez2017-12-071-6/+69
* intel/fs: Don't let undefined values prevent copy propagation.Francisco Jerez2017-12-071-3/+47
* intel/fs: Restrict live intervals to the subset possibly reachable from any d...Francisco Jerez2017-12-072-4/+42
* intel/fs: Teach instruction scheduler about GRF bank conflict cycles.Francisco Jerez2017-12-073-2/+23
* intel/fs: Implement GRF bank conflict mitigation pass.Francisco Jerez2017-12-074-0/+897
* i965/fs: Use untyped_surface_read for 16-bit load_ssboJose Maria Casanova Crespo2017-12-061-7/+20
* i965/fs: Optimize 16-bit SSBO stores by packing two into a 32-bit regJose Maria Casanova Crespo2017-12-061-15/+43
* i965/fs: Enables 16-bit load_ubo with samplerJason Ekstrand2017-12-061-7/+14
* i965/fs: Helpers for un/shuffle 16-bit pairs in 32-bit componentsJose Maria Casanova Crespo2017-12-062-0/+71
* i965/fs: Use byte scattered read for 16-bit load_ssboJose Maria Casanova Crespo2017-12-061-1/+13
* i965/fs: Add byte scattered read message and fs supportJose Maria Casanova Crespo2017-12-069-1/+94
* i965/fs: Predicate byte scattered writes if neededAlejandro Piñeiro2017-12-061-1/+14
* i965/fs: Use byte_scattered_write on 16-bit store_ssboAlejandro Piñeiro2017-12-061-20/+45
* i965/fs: Add byte scattered write message and fs supportJose Maria Casanova Crespo2017-12-069-0/+118
* i965/fs: Add remove_extra_rounding_modes optimizationAlejandro Piñeiro2017-12-063-0/+39
* i965/fs: Enable rounding mode on f2f16 opsAlejandro Piñeiro2017-12-061-0/+18
* i965/fs: Define new shader opcode to set rounding modesAlejandro Piñeiro2017-12-065-0/+62
* i965: Add support for control registerJose Maria Casanova Crespo2017-12-061-0/+6
* i965/fs: Handle 32-bit to 16-bit conversionsAlejandro Piñeiro2017-12-061-0/+25
* i965/fs: Remove BRW_REGISTER_TYPE_HF assert at get_exec_typeAlejandro Piñeiro2017-12-061-3/+0
* i965: Support for 16-bit base types in helper functionsJose Maria Casanova Crespo2017-12-063-0/+25
* i965/vec4: Handle 16-bit types at type_size_xvec4Alejandro Piñeiro2017-12-061-0/+3
* intel/compiler: Implement WaClearTDRRegBeforeEOTForNonPS.Rafael Antognolli2017-12-012-0/+19
* i965/vec4: use a temp register to compute offsets for pull loadsIago Toral Quiroga2017-11-301-1/+3
* i965/vec4: fix splitting of interleaved attributesIago Toral Quiroga2017-11-241-1/+6
* i965/fs: Check ADD/MAD with immediates in satprop unit testMatt Turner2017-11-211-1/+125
* i965/fs: Handle negating immediates on MADs when propagating saturatesMatt Turner2017-11-211-2/+8
* intel: fix disasm_info memory leaksTapani Pälli2017-11-212-2/+2
* i965: Stop including brw_cfg.h in brw_disasm_info.hJason Ekstrand2017-11-171-1/+5
* i965: Correct disasm_info usage in eu_validate testAndres Gomez2017-11-181-6/+6
* i965: Rename intel_asm_annotation -> brw_disasm_infoMatt Turner2017-11-175-5/+5
* i965: Rewrite disassembly annotation codeMatt Turner2017-11-179-150/+152
* i965: Simplify annotation_insert_error()Matt Turner2017-11-171-9/+6
* i965: Move common code out of #ifdefMatt Turner2017-11-172-9/+4
* intel: Drop mtypes.h include from brw_compiler.h.Kenneth Graunke2017-11-151-1/+0
* i965: Use nir_lower_atomics_to_ssbos and delete ABO compiler code.Kenneth Graunke2017-11-155-128/+0
* Revert "intel/fs: Use a pure vertical stride for large register strides"Matt Turner2017-11-141-13/+3
* i965/fs: Fix extract_i8/u8 to a 64-bit destinationMatt Turner2017-11-141-2/+23
* i965/fs: Split all 32->64-bit MOVs on CHV, BXT, GLKMatt Turner2017-11-141-4/+4
* intel/nir: Use the correct indirect lowering masks in link_shadersJason Ekstrand2017-11-081-6/+4
* intel/nir: Break the linking code into a helper in brw_nir.cJason Ekstrand2017-11-082-0/+36
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