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* i965: Drop mark_surface_used mechanism.Kenneth Graunke2019-01-137-100/+0
* intel/nir: Call nir_opt_deref in brw_nir_optimizeJason Ekstrand2019-01-121-0/+1
* intel/peephole_ffma: Fix swizzle propagationJason Ekstrand2019-01-111-4/+7
* i965: Compile fp64 software routines and lower double-opsMatt Turner2019-01-091-22/+70
* intel/compiler: Heap-allocate temporary storageMatt Turner2019-01-091-3/+5
* intel/compiler: Expand size of the 'nr' fieldMatt Turner2019-01-091-4/+3
* intel/compiler: Prevent warnings in the following patchMatt Turner2019-01-0911-36/+38
* intel/compiler: Rearrange code to avoid future problemsMatt Turner2019-01-091-3/+4
* intel/compiler: Avoid false positive assertionsMatt Turner2019-01-091-6/+6
* intel/compiler: Split 64-bit MOV-indirects if neededMatt Turner2019-01-091-1/+2
* intel/compiler: Lower 64-bit MOV/SEL operationsMatt Turner2019-01-091-1/+49
* intel/fs: Remove FS_OPCODE_UNPACK_HALF_2x16_SPLIT opcodes.Francisco Jerez2019-01-096-47/+4
* intel/fs: Remove nasty open-coded CHV/BXT 64-bit workarounds.Francisco Jerez2019-01-092-145/+12
* intel/fs: Remove existing lower_conversions pass.Francisco Jerez2019-01-094-138/+1
* intel/fs: Introduce regioning lowering pass.Francisco Jerez2019-01-095-19/+417
* intel/fs: Constify fs_inst::can_do_source_mods().Francisco Jerez2019-01-092-2/+2
* intel/fs: Respect CHV/BXT regioning restrictions in copy propagation pass.Francisco Jerez2019-01-092-0/+38
* intel/eu/gen7: Fix brw_MOV() with DF destination and strided source.Francisco Jerez2019-01-091-7/+4
* intel/fs: Fix bug in lower_simd_width while splitting an instruction which wa...Francisco Jerez2019-01-091-2/+5
* intel/fs: Implement quad swizzles on ICL+.Francisco Jerez2019-01-093-18/+97
* intel/fs: Handle source modifiers in lower_integer_multiplication().Francisco Jerez2019-01-092-2/+37
* nir: rename global/local to private/function memoryKarol Herbst2019-01-081-5/+5
* nir: rename nir_link_constant_varyings() nir_link_opt_varyings()Timothy Arceri2019-01-021-1/+1
* intel/compiler: move nir_lower_bool_to_int32 before nir_lower_locals_to_regsIago Toral Quiroga2018-12-201-2/+2
* intel/compiler: More peephole_select for pre-Gen6Ian Romanick2018-12-171-2/+2
* nir/opt_peephole_select: Don't peephole_select expensive math instructionsIan Romanick2018-12-171-2/+2
* intel/compiler: More peephole selectIan Romanick2018-12-171-1/+14
* nir/opt_peephole_select: Don't try to remove flow control around indirect loadsIan Romanick2018-12-171-1/+12
* i965/vec4: Propagate conditional modifiers from more compares to other comparesIan Romanick2018-12-171-3/+100
* i965/fs: Eliminate unary op on operand of compare-with-zeroIan Romanick2018-12-172-17/+14
* i965/vec4/dce: Don't narrow the write mask if the flags are usedIan Romanick2018-12-173-10/+203
* i965/vec4: Silence unused parameter warnings in vec4 compiler testsIan Romanick2018-12-173-9/+9
* nir: Add a bool to int32 lowering passJason Ekstrand2018-12-161-0/+2
* nir: Rename Boolean-related opcodes to include 32 in the nameJason Ekstrand2018-12-163-102/+102
* nir: Move intel's half-float image store lowering to to nir_format.h.Eric Anholt2018-12-131-8/+2
* Revert "intel: Simplify the half-float packing in image load/store lowering."Eric Anholt2018-12-131-2/+8
* i965: Enable nir_opt_idiv_const for 32 and 64-bit integersJason Ekstrand2018-12-131-1/+3
* i965/vec4: Implement nir_op_uadd_satJason Ekstrand2018-12-131-0/+6
* i965/fs: Implement nir_op_uadd_satIan Romanick2018-12-131-0/+5
* intel: Simplify the half-float packing in image load/store lowering.Eric Anholt2018-12-121-8/+2
* nir: Pull some of intel's image load/store format conversion to nir_format.hEric Anholt2018-12-121-18/+2
* intel/compiler: do not copy-propagate strided regions to ddx/ddy argumentsIago Toral Quiroga2018-12-121-0/+21
* intel/fs: Support min_lod parameters on texture instructionsJason Ekstrand2018-12-114-2/+31
* intel/ir: Don't allow allocating zero registersJason Ekstrand2018-12-111-0/+1
* i965/fs: Handle V/UV immediates in dump_instructions()Matt Turner2018-12-101-0/+5
* intel/compiler: Always print flag subregister numberSagar Ghuge2018-12-101-7/+6
* intel/compiler: Set swizzle to BRW_SWIZZLE_XXXX for scalar regionSagar Ghuge2018-12-101-1/+18
* nir: Make boolean conversions sized just like the othersJason Ekstrand2018-12-052-11/+17
* mesa: Revert INTEL_fragment_shader_ordering supportMatt Turner2018-12-031-1/+0
* intel/compiler: Use nir's info when checking uses_streams.Kenneth Graunke2018-11-281-1/+1
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