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* nir: Add a nir_src_as_intrinsic() helperJason Ekstrand2019-04-181-11/+4
* nir: Rework nir_src_as_alu_instr to not take a pointerJason Ekstrand2019-04-181-6/+4
* intel/compiler: validate region restrictions for mixed float modeIago Toral Quiroga2019-04-182-0/+880
* intel/compiler: validate conversions between 64-bit and 8-bit typesIago Toral Quiroga2019-04-182-0/+105
* intel/compiler: validate region restrictions for half-float conversionsIago Toral Quiroga2019-04-182-1/+270
* intel/compiler: also set F execution type for mixed float mode in BDWIago Toral Quiroga2019-04-181-16/+20
* intel/compiler: implement SIMD16 restrictions for mixed-float instructionsIago Toral Quiroga2019-04-181-0/+72
* intel/compiler: skip MAD algebraic optimization for half-float or mixed modeIago Toral Quiroga2019-04-181-0/+4
* intel/compiler: remove inexact algebraic optimizations from the backendIago Toral Quiroga2019-04-181-38/+1
* intel/compiler: fix cmod propagation for non 32-bit typesIago Toral Quiroga2019-04-181-4/+9
* intel/compiler: add a brw_reg_type_is_integer helperIago Toral Quiroga2019-04-181-0/+18
* intel/compiler: implement is_zero, is_one, is_negative_one for 8-bit/16-bitIago Toral Quiroga2019-04-181-0/+26
* intel/compiler: generalize the combine constants passIago Toral Quiroga2019-04-181-22/+212
* intel/eu: force stride of 2 on NULL register for Byte instructionsIago Toral Quiroga2019-04-181-0/+11
* intel/compiler: ask for an integer type if requesting an 8-bit typeIago Toral Quiroga2019-04-181-2/+3
* intel/compiler: rework conversion opcodesIago Toral Quiroga2019-04-181-19/+22
* intel/compiler: activate 16-bit bit-size lowerings also for 8-bitIago Toral Quiroga2019-04-181-1/+1
* intel/compiler: split is_partial_write() into two variantsIago Toral Quiroga2019-04-1811-30/+54
* intel/compiler: workaround for SIMD8 half-float MAD in gen8Iago Toral Quiroga2019-04-181-11/+28
* intel/compiler: fix ddy for half-float in BroadwellIago Toral Quiroga2019-04-181-2/+15
* intel/compiler: fix ddx and ddy for 16-bit floatIago Toral Quiroga2019-04-181-19/+18
* intel/compiler: set correct precision fields for 3-source float instructionsIago Toral Quiroga2019-04-181-0/+16
* intel/compiler: allow half-float on 3-source instructions since gen8Iago Toral Quiroga2019-04-181-1/+2
* intel/compiler: don't compact 3-src instructions with Src1Type or Src2Type bitsIago Toral Quiroga2019-04-181-1/+4
* intel/compiler: add new half-float register type for 3-src instructionsIago Toral Quiroga2019-04-181-0/+4
* intel/compiler: add instruction setters for Src1Type and Src2Type.Iago Toral Quiroga2019-04-181-0/+2
* intel/compiler: drop unnecessary temporary from 32-bit fsign implementationIago Toral Quiroga2019-04-181-3/+2
* intel/compiler: implement 16-bit fsignIago Toral Quiroga2019-04-181-1/+16
* intel/compiler: handle extended math restrictions for half-floatIago Toral Quiroga2019-04-183-12/+34
* intel/compiler: lower some 16-bit float operations to 32-bitIago Toral Quiroga2019-04-181-0/+5
* intel/compiler: assert restrictions on conversions to half-floatIago Toral Quiroga2019-04-181-2/+3
* intel/compiler: handle b2i/b2f with other integer conversion opcodesIago Toral Quiroga2019-04-181-8/+8
* intel/compiler: split float to 64-bit opcodes from int to 64-bitIago Toral Quiroga2019-04-181-0/+7
* intel/compiler: add a NIR pass to lower conversionsIago Toral Quiroga2019-04-184-0/+174
* intel/compiler/icl: Use tcs barrier id bits 24:30 instead of 24:27Topi Pohjolainen2019-04-171-7/+17
* i965: Move program key debugging to the compiler.Kenneth Graunke2019-04-163-0/+238
* intel/compiler: Do not reswizzle dst if instruction writes to flag registerDanylo Piliaiev2019-04-161-0/+6
* nir: make nir_const_value scalarKarol Herbst2019-04-143-16/+16
* nir/builder: Add a nir_imm_zero helperJason Ekstrand2019-04-141-10/+1
* intel/nir: use nir_src_is_const and nir_src_as_uintKarol Herbst2019-04-141-6/+4
* intel/nir: Take a nir_tex_instr and src index in brw_texture_offsetJason Ekstrand2019-04-144-27/+21
* intel/fs: Remove unused condition from opt_algebraic caseSagar Ghuge2019-04-121-5/+0
* nir/i965/freedreno/vc4: add a bindless bool to type size functionsTimothy Arceri2019-04-124-25/+30
* nir: move brw_nir_rewrite_image_intrinsic into common codeKarol Herbst2019-04-121-41/+0
* intel/common: move gen_debug to intel/devMark Janes2019-04-1016-16/+16
* intel/fs: Use NIR_PASS_V when lowering CS intrinsicsCaio Marcelo de Oliveira Filho2019-04-081-3/+4
* intel/fs: Don't loop when lowering CS intrinsicsCaio Marcelo de Oliveira Filho2019-04-081-15/+10
* intel/fs: Add support for CS to group invocations in quadsCaio Marcelo de Oliveira Filho2019-04-083-16/+103
* intel/fs: Use TEX_LOGICAL whenever implicit lod is supportedCaio Marcelo de Oliveira Filho2019-04-081-2/+6
* nir/radv: remove restrictions on opt_if_loop_last_continue()Timothy Arceri2019-04-091-1/+1
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