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* intel/eu: Use EXECUTE_1 for JMPIJason Ekstrand2017-10-252-2/+1
* i965/fs: Add brw_reg_type_from_bit_size utility methodAlejandro Piñeiro2017-10-251-5/+64
* i965/fs/nir: Use the nir_src_bit_size helperJason Ekstrand2017-10-251-9/+3
* intel/fs: Handle flag read/write aliasing in needs_src_copyJason Ekstrand2017-10-251-1/+3
* intel/nir: Zero local index const struct for valgrind & nir_serializeJordan Justen2017-10-251-0/+1
* meson: extract out variable for nir_algebraic.pyRob Clark2017-10-241-1/+1
* i965: Fix memmem compiler warnings.Eric Anholt2017-10-241-1/+2
* i965/fs: Use align1 mode on ternary instructions on Gen10+Matt Turner2017-10-201-4/+8
* i965: Add align1 ternary instruction emission supportMatt Turner2017-10-201-55/+160
* i965: Add align1 ternary instruction disassembler supportMatt Turner2017-10-202-75/+288
* i965: Add align1 ternary instruction-word supportMatt Turner2017-10-201-0/+108
* i965: Add align1 ternary instruction support to conversion functionsMatt Turner2017-10-204-34/+101
* i965: Add align1 ternary instruction field encodingsMatt Turner2017-10-201-0/+35
* i965: Add functions to abstract access to 3src register typesMatt Turner2017-10-202-20/+23
* i965: Rename brw_inst's functions that access the 3src register typeMatt Turner2017-10-203-18/+18
* i965: Rename brw_inst 3src functions in preparation for align1Matt Turner2017-10-204-86/+92
* i965: Print subreg in units of type-size on ternary instructionsMatt Turner2017-10-201-5/+26
* i965: Add functions for brw_reg_type <-> hw 3src typeMatt Turner2017-10-202-0/+58
* i965: Move brw_reg_type_is_floating_point to brw_reg_type.hMatt Turner2017-10-202-13/+15
* nir: Get rid of nir_shader::stageJason Ekstrand2017-10-206-21/+21
* i965/vec4: remove setting default LOD in the backendSamuel Iglesias Gonsálvez2017-10-202-21/+0
* i965/fs: remove setting default LOD in the backendSamuel Iglesias Gonsálvez2017-10-201-9/+0
* i965: Use is_scheduling_barrier instead of schedule_node::is_barrier.Kenneth Graunke2017-10-191-22/+10
* i965: Move fs_inst::has_side_effects()'s eot check to the parent class.Kenneth Graunke2017-10-195-9/+3
* intel/cs: Make thread_local_id a regular builtin paramJason Ekstrand2017-10-123-28/+29
* intel/compiler: Allocate pull_param in assign_constant_locationsJason Ekstrand2017-10-122-6/+14
* intel: Allocate prog_data::[pull_]param deeper inside the compilerJason Ekstrand2017-10-122-4/+4
* intel/vs: Grow the param array for clip planesJason Ekstrand2017-10-122-0/+14
* intel/cs: Grow prog_data::param on-demand for thread_local_id_indexJason Ekstrand2017-10-122-15/+9
* intel/compiler: Make brw_nir_lower_intrinsics compute-specificJason Ekstrand2017-10-124-18/+12
* intel/compiler: Add a helper for growing the prog_data::param arrayJason Ekstrand2017-10-121-0/+13
* intel/compiler: Add a flag for pull constant supportJason Ekstrand2017-10-123-2/+11
* i965: Store image_param in brw_context instead of prog_dataJason Ekstrand2017-10-121-4/+0
* intel: Rewrite the world of push/pull paramsJason Ekstrand2017-10-128-40/+90
* i965: Fix output register sizes when multiple variables share a slot.Kenneth Graunke2017-10-101-5/+18
* i965: Don't try to decode types for non-existent src1.Kenneth Graunke2017-10-101-1/+2
* i965/tes: account for the fact that dvec3/4 inputs take two slotsIago Toral Quiroga2017-10-101-2/+7
* intel/compiler: Don't propagate cmod into integer multipliesJason Ekstrand2017-10-052-0/+34
* intel/compiler: Don't cmod propagate into a saturated operationJason Ekstrand2017-10-052-0/+16
* i965: Validate "Special Requirements for Handling Double Precision Data Types"Matt Turner2017-10-042-0/+792
* i965: Fix and enable forgotten validation testMatt Turner2017-10-041-14/+17
* i965: Only insert error message if not already presentMatt Turner2017-10-041-5/+13
* i965: Avoid validation error when src1 is not presentMatt Turner2017-10-041-1/+1
* i965: Remove validate_reg()Matt Turner2017-10-041-80/+0
* i965: Add and use STRIDE and WIDTH macrosMatt Turner2017-10-041-18/+15
* i965: Add GLK, CFL, CNL to test_eu_validate.cMatt Turner2017-10-041-0/+7
* i965: Fix support for disassembling 64-bit integer immediatesMatt Turner2017-10-041-2/+2
* i965/fs: Rewrite fsign64 to skip the float -> double conversionMatt Turner2017-10-041-41/+9
* i965/fs: Unpack count argument to 64-bit shift ops on AtomMatt Turner2017-10-041-6/+28
* i965/fs: Don't apply POW/FDIV workaround on Gen10+Matt Turner2017-10-041-0/+1
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