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* i965/nir: do int64 lowering before optimizationIago Toral Quiroga2018-02-061-4/+12
* i965: Move mistakenly placed lineMatt Turner2018-02-051-1/+1
* nir: add vs_inputs_dual_locations compiler optionTimothy Arceri2018-01-301-0/+3
* compiler: tidy up double_inputs_read usesTimothy Arceri2018-01-301-1/+1
* i965/gen10: Re-enable push constants.Rafael Antognolli2018-01-261-9/+0
* i965/fs: Reset the register file to VGRF in lower_integer_multiplicationJason Ekstrand2018-01-251-5/+10
* i965: Drop render_target_start from binding table struct.Kenneth Graunke2018-01-222-5/+2
* intel/fs: Optimize and simplify the copy propagation dataflow logic.Francisco Jerez2018-01-171-24/+11
* meson: Use dependencies for nirDylan Baker2018-01-111-6/+6
* meson: Use consistent style for testsDylan Baker2018-01-111-8/+11
* meson: Use consistent styleDylan Baker2018-01-111-2/+4
* i965: Use UD types for gl_SampleID setupJason Ekstrand2018-01-111-3/+3
* i965/fs: Use UW types when using V immediatesJason Ekstrand2018-01-112-5/+5
* Revert "Revert "i965/fs: Use align1 mode on ternary instructions on Gen10+""Matt Turner2018-01-111-4/+8
* i965/fs: Add/use functions to convert to 3src_align1 vstride/hstrideMatt Turner2018-01-111-28/+41
* i965/nir: add a helper to lower gl_PatchVerticesIn to a uniformIago Toral Quiroga2018-01-101-0/+2
* i965: Drop support for the legacy SNORM -> Float equation.Kenneth Graunke2018-01-027-41/+13
* i965: Combine {VS,FS}_OPCODE_GET_BUFFER_SIZE opcodes.Kenneth Graunke2017-12-308-19/+14
* Revert "i965/fs: Use align1 mode on ternary instructions on Gen10+"Anuj Phogat2017-12-221-8/+4
* intel/fs: Initialize fs_visitor::grf_used on construction.Francisco Jerez2017-12-211-0/+1
* intel/fs/bank_conflicts: Use posix_memalign() instead of overaligned new to o...Francisco Jerez2017-12-211-6/+16
* intel/compiler/gen10: Disable push constants.Rafael Antognolli2017-12-191-0/+9
* intel/fs/bank_conflicts: Don't touch Gen7 MRF hack registers.Francisco Jerez2017-12-123-7/+19
* i965/fs: Handle !supports_pull_constants and push UBOs properlyJason Ekstrand2017-12-081-1/+1
* i965/fs: Rewrite assign_constant_locationsJason Ekstrand2017-12-081-133/+185
* intel/cfg: Represent divergent control flow paths caused by non-uniform loop ...Francisco Jerez2017-12-071-6/+69
* intel/fs: Don't let undefined values prevent copy propagation.Francisco Jerez2017-12-071-3/+47
* intel/fs: Restrict live intervals to the subset possibly reachable from any d...Francisco Jerez2017-12-072-4/+42
* intel/fs: Teach instruction scheduler about GRF bank conflict cycles.Francisco Jerez2017-12-073-2/+23
* intel/fs: Implement GRF bank conflict mitigation pass.Francisco Jerez2017-12-074-0/+897
* i965/fs: Use untyped_surface_read for 16-bit load_ssboJose Maria Casanova Crespo2017-12-061-7/+20
* i965/fs: Optimize 16-bit SSBO stores by packing two into a 32-bit regJose Maria Casanova Crespo2017-12-061-15/+43
* i965/fs: Enables 16-bit load_ubo with samplerJason Ekstrand2017-12-061-7/+14
* i965/fs: Helpers for un/shuffle 16-bit pairs in 32-bit componentsJose Maria Casanova Crespo2017-12-062-0/+71
* i965/fs: Use byte scattered read for 16-bit load_ssboJose Maria Casanova Crespo2017-12-061-1/+13
* i965/fs: Add byte scattered read message and fs supportJose Maria Casanova Crespo2017-12-069-1/+94
* i965/fs: Predicate byte scattered writes if neededAlejandro Piñeiro2017-12-061-1/+14
* i965/fs: Use byte_scattered_write on 16-bit store_ssboAlejandro Piñeiro2017-12-061-20/+45
* i965/fs: Add byte scattered write message and fs supportJose Maria Casanova Crespo2017-12-069-0/+118
* i965/fs: Add remove_extra_rounding_modes optimizationAlejandro Piñeiro2017-12-063-0/+39
* i965/fs: Enable rounding mode on f2f16 opsAlejandro Piñeiro2017-12-061-0/+18
* i965/fs: Define new shader opcode to set rounding modesAlejandro Piñeiro2017-12-065-0/+62
* i965: Add support for control registerJose Maria Casanova Crespo2017-12-061-0/+6
* i965/fs: Handle 32-bit to 16-bit conversionsAlejandro Piñeiro2017-12-061-0/+25
* i965/fs: Remove BRW_REGISTER_TYPE_HF assert at get_exec_typeAlejandro Piñeiro2017-12-061-3/+0
* i965: Support for 16-bit base types in helper functionsJose Maria Casanova Crespo2017-12-063-0/+25
* i965/vec4: Handle 16-bit types at type_size_xvec4Alejandro Piñeiro2017-12-061-0/+3
* intel/compiler: Implement WaClearTDRRegBeforeEOTForNonPS.Rafael Antognolli2017-12-012-0/+19
* i965/vec4: use a temp register to compute offsets for pull loadsIago Toral Quiroga2017-11-301-1/+3
* i965/vec4: fix splitting of interleaved attributesIago Toral Quiroga2017-11-241-1/+6
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