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* intel/eu/validate/gen12: Don't blow up on indirect src0.Jason Ekstrand2019-10-111-1/+2
* intel/eu/validate/gen12: Validation fixes for SEND instruction.Francisco Jerez2019-10-111-22/+28
* intel/eu/validate/gen12: Fix validation of SYNC instruction.Francisco Jerez2019-10-111-1/+1
* intel/eu/validate/gen12: Implement integer multiply restrictions in EU valida...Francisco Jerez2019-10-111-0/+33
* intel/ir: Lower fpow on Gen12.Jordan Justen2019-10-111-0/+1
* intel/fs/gen12: Don't support source mods for 32x16 integer multiply.Francisco Jerez2019-10-111-0/+18
* intel/disasm: Disassemble register file of split SEND sources.Francisco Jerez2019-10-111-1/+4
* intel/disasm: Don't disassemble saturate control on SEND instructions.Francisco Jerez2019-10-111-2/+4
* intel/disasm/gen12: Disassemble Gen12 SEND instructions.Francisco Jerez2019-10-111-4/+18
* intel/disasm/gen12: Disassemble Gen12 SYNC instruction.Francisco Jerez2019-10-111-0/+14
* intel/disasm/gen12: Disassemble three-source instruction source and destinati...Francisco Jerez2019-10-111-13/+32
* intel/disasm/gen12: Fix disassembly of some common instruction controls.Francisco Jerez2019-10-111-4/+9
* intel/disasm/gen12: Disassemble software scoreboard information.Francisco Jerez2019-10-111-0/+16
* intel/fs/gen12: Demodernize software scoreboard lowering pass.Francisco Jerez2019-10-111-81/+163
* intel/fs/gen12: Introduce software scoreboard lowering pass.Francisco Jerez2019-10-114-0/+945
* intel/fs/gen12: Add scheduling information to the IR.Francisco Jerez2019-10-112-0/+3
* intel/eu/gen12: Set SWSB annotations in hand-crafted assembly.Francisco Jerez2019-10-112-5/+91
* intel/eu/gen12: Add tracking of default SWSB state to the current brw_codegen...Francisco Jerez2019-10-113-0/+18
* intel/eu/gen12: Add auxiliary type to represent SWSB information during codegen.Francisco Jerez2019-10-111-0/+148
* intel/fs/gen12: Add codegen support for the SYNC instruction.Francisco Jerez2019-10-114-3/+19
* intel/ir/gen12: Add SYNC hardware instruction.Francisco Jerez2019-10-113-0/+3
* intel/eu/gen12: Don't set thread control, it's gone.Francisco Jerez2019-10-111-2/+4
* intel/eu/gen12: Don't set DD control, it's gone.Francisco Jerez2019-10-112-6/+12
* intel/eu/gen12: Use SEND instruction for split sends.Francisco Jerez2019-10-112-2/+3
* intel/eu/gen12: Codegen SEND descriptor regions correctly.Francisco Jerez2019-10-112-6/+14
* intel/eu/gen12: Codegen pathological SEND source and destination regions.Francisco Jerez2019-10-111-7/+39
* intel/eu/gen12: Codegen control flow instructions correctly.Francisco Jerez2019-10-111-6/+9
* intel/eu/gen12: Codegen three-source instruction source and destination regions.Francisco Jerez2019-10-112-24/+42
* intel/eu/gen12: Fix codegen of immediate source regions.Francisco Jerez2019-10-111-1/+1
* intel/eu/gen12: Add Gen12 opcode descriptions to the table.Francisco Jerez2019-10-111-24/+47
* intel/eu/gen11+: Mark dot product opcodes as unsupported on opcode_descs table.Francisco Jerez2019-10-111-4/+4
* intel/eu/gen12: Implement datatype binary encoding.Francisco Jerez2019-10-111-7/+55
* intel/eu/gen12: Implement immediate 64 bit constant encoding.Sagar Ghuge2019-10-111-2/+13
* intel/eu/gen12: Implement compact instruction binary encoding.Francisco Jerez2019-10-111-39/+49
* intel/eu/gen12: Implement indirect region binary encoding.Francisco Jerez2019-10-111-8/+15
* intel/eu/gen12: Implement SEND instruction binary encoding.Francisco Jerez2019-10-111-69/+135
* intel/eu/gen12: Implement control flow instruction binary encoding.Francisco Jerez2019-10-111-0/+6
* intel/eu/gen12: Implement three-source instruction binary encoding.Francisco Jerez2019-10-111-67/+85
* intel/eu/gen12: Implement basic instruction binary encoding.Francisco Jerez2019-10-111-47/+51
* intel/eu/gen12: Add sanity-check asserts to brw_inst_bits() and brw_inst_set_...Francisco Jerez2019-10-111-0/+2
* intel/eu/gen12: Extend brw_inst.h macros for Gen12 support.Francisco Jerez2019-10-111-202/+346
* intel/ir: Represent physical edge of unconditional CONTINUE instruction.Francisco Jerez2019-10-111-0/+2
* intel/ir: Represent physical edge of ELSE instruction.Francisco Jerez2019-10-111-0/+1
* intel/ir: Represent logical edge of BREAK instruction.Francisco Jerez2019-10-111-0/+1
* intel/ir: Add helper function to push block onto CFG analysis stack.Francisco Jerez2019-10-111-4/+13
* intel/ir: Represent physical and logical subsets of the CFG.Francisco Jerez2019-10-113-40/+81
* intel/ir: Drop hard-coded correspondence between IR and HW opcodes.Francisco Jerez2019-10-112-95/+85
* intel/eu: Encode and decode native instruction opcodes from/to IR opcodes.Francisco Jerez2019-10-117-15/+41
* intel/eu: Rework opcode description tables to allow efficient look-up by eith...Francisco Jerez2019-10-114-303/+165
* intel/eu: Fix up various type conversions in brw_eu.c that are illegal C++.Francisco Jerez2019-10-114-13/+13
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