| Commit message (Expand) | Author | Age | Files | Lines |
* | intel/compiler: add new half-float register type for 3-src instructions | Iago Toral Quiroga | 2019-04-18 | 1 | -0/+4 |
* | intel/compiler: add instruction setters for Src1Type and Src2Type. | Iago Toral Quiroga | 2019-04-18 | 1 | -0/+2 |
* | intel/compiler: drop unnecessary temporary from 32-bit fsign implementation | Iago Toral Quiroga | 2019-04-18 | 1 | -3/+2 |
* | intel/compiler: implement 16-bit fsign | Iago Toral Quiroga | 2019-04-18 | 1 | -1/+16 |
* | intel/compiler: handle extended math restrictions for half-float | Iago Toral Quiroga | 2019-04-18 | 3 | -12/+34 |
* | intel/compiler: lower some 16-bit float operations to 32-bit | Iago Toral Quiroga | 2019-04-18 | 1 | -0/+5 |
* | intel/compiler: assert restrictions on conversions to half-float | Iago Toral Quiroga | 2019-04-18 | 1 | -2/+3 |
* | intel/compiler: handle b2i/b2f with other integer conversion opcodes | Iago Toral Quiroga | 2019-04-18 | 1 | -8/+8 |
* | intel/compiler: split float to 64-bit opcodes from int to 64-bit | Iago Toral Quiroga | 2019-04-18 | 1 | -0/+7 |
* | intel/compiler: add a NIR pass to lower conversions | Iago Toral Quiroga | 2019-04-18 | 4 | -0/+174 |
* | intel/compiler/icl: Use tcs barrier id bits 24:30 instead of 24:27 | Topi Pohjolainen | 2019-04-17 | 1 | -7/+17 |
* | i965: Move program key debugging to the compiler. | Kenneth Graunke | 2019-04-16 | 3 | -0/+238 |
* | intel/compiler: Do not reswizzle dst if instruction writes to flag register | Danylo Piliaiev | 2019-04-16 | 1 | -0/+6 |
* | nir: make nir_const_value scalar | Karol Herbst | 2019-04-14 | 3 | -16/+16 |
* | nir/builder: Add a nir_imm_zero helper | Jason Ekstrand | 2019-04-14 | 1 | -10/+1 |
* | intel/nir: use nir_src_is_const and nir_src_as_uint | Karol Herbst | 2019-04-14 | 1 | -6/+4 |
* | intel/nir: Take a nir_tex_instr and src index in brw_texture_offset | Jason Ekstrand | 2019-04-14 | 4 | -27/+21 |
* | intel/fs: Remove unused condition from opt_algebraic case | Sagar Ghuge | 2019-04-12 | 1 | -5/+0 |
* | nir/i965/freedreno/vc4: add a bindless bool to type size functions | Timothy Arceri | 2019-04-12 | 4 | -25/+30 |
* | nir: move brw_nir_rewrite_image_intrinsic into common code | Karol Herbst | 2019-04-12 | 1 | -41/+0 |
* | intel/common: move gen_debug to intel/dev | Mark Janes | 2019-04-10 | 16 | -16/+16 |
* | intel/fs: Use NIR_PASS_V when lowering CS intrinsics | Caio Marcelo de Oliveira Filho | 2019-04-08 | 1 | -3/+4 |
* | intel/fs: Don't loop when lowering CS intrinsics | Caio Marcelo de Oliveira Filho | 2019-04-08 | 1 | -15/+10 |
* | intel/fs: Add support for CS to group invocations in quads | Caio Marcelo de Oliveira Filho | 2019-04-08 | 3 | -16/+103 |
* | intel/fs: Use TEX_LOGICAL whenever implicit lod is supported | Caio Marcelo de Oliveira Filho | 2019-04-08 | 1 | -2/+6 |
* | nir/radv: remove restrictions on opt_if_loop_last_continue() | Timothy Arceri | 2019-04-09 | 1 | -1/+1 |
* | intel/compiler: use defined size for vector components | Dave Airlie | 2019-04-03 | 1 | -1/+1 |
* | intel/compiler: Use partial redundancy elimination for compares | Ian Romanick | 2019-03-28 | 1 | -0/+20 |
* | intel/fs: Make alpha test work with MRT and sample mask | Danylo Piliaiev | 2019-03-25 | 1 | -18/+17 |
* | i965,iris,anv: Make alpha to coverage work with sample mask | Danylo Piliaiev | 2019-03-25 | 4 | -4/+99 |
* | compiler/nir: add lowering for 16-bit flrp | Iago Toral Quiroga | 2019-03-25 | 1 | -0/+1 |
* | compiler/nir: add lowering option for 16-bit fmod | Iago Toral Quiroga | 2019-03-25 | 1 | -0/+1 |
* | intel/compiler: handle GLSL_TYPE_INTERFACE as GLSL_TYPE_STRUCT | Caio Marcelo de Oliveira Filho | 2019-03-23 | 3 | -3/+3 |
* | anv,radv,turnip: Lower TG4 offsets with nir_lower_tex | Jason Ekstrand | 2019-03-21 | 1 | -0/+1 |
* | intel/nir: Lower array-deref-of-vector UBO and SSBO loads | Jason Ekstrand | 2019-03-15 | 1 | -0/+11 |
* | i965: Stop setting LowerBuferInterfaceBlocks | Jason Ekstrand | 2019-03-15 | 1 | -1/+0 |
* | i965: Disable ARB_fragment_shader_interlock for platforms prior to GEN9 | Plamena Manolova | 2019-03-14 | 1 | -0/+1 |
* | intel/nir: Combine store_derefs to improve code from SPIR-V | Caio Marcelo de Oliveira Filho | 2019-03-13 | 1 | -0/+1 |
* | intel/nir: Combine store_derefs after vectorizing IO | Caio Marcelo de Oliveira Filho | 2019-03-13 | 1 | -0/+1 |
* | nir: Add a pass to combine store_derefs to same vector | Caio Marcelo de Oliveira Filho | 2019-03-13 | 1 | -0/+1 |
* | intel/fs: Fix opt_peephole_csel to not throw away saturates. | Kenneth Graunke | 2019-03-12 | 1 | -0/+1 |
* | intel/nir: Vectorize all IO | Jason Ekstrand | 2019-03-12 | 1 | -0/+17 |
* | intel/nir: Move lower_mem_access_bit_sizes to postprocess_nir | Jason Ekstrand | 2019-03-08 | 1 | -2/+1 |
* | intel/compiler: silence unitialized variable warning in opt_vector_float() | Brian Paul | 2019-03-08 | 1 | -1/+1 |
* | intel/nir: Move 64-bit lowering later | Jason Ekstrand | 2019-03-06 | 1 | -21/+13 |
* | nir/lower_doubles: Inline functions directly in lower_doubles | Jason Ekstrand | 2019-03-06 | 2 | -19/+6 |
* | intel/nir: Drop an unneeded lower_constant_initializers call | Jason Ekstrand | 2019-03-06 | 1 | -2/+0 |
* | intel/debug: Add a debug flag to force software fp64 | Jason Ekstrand | 2019-03-06 | 1 | -1/+1 |
* | intel/fs: Fix extract_u8 of an odd byte from a 64-bit integer | Ian Romanick | 2019-03-06 | 1 | -0/+7 |
* | intel/fs: nir_op_extract_i8 extracts a byte, not a word | Ian Romanick | 2019-03-06 | 1 | -2/+4 |