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* intel/compiler: Cast to target type before shifting leftMichel Dänzer2019-10-241-1/+1
* intel/compiler: Don't left-shift by >= the number of bits of the typeMichel Dänzer2019-10-241-2/+2
* intel/compiler: Refactor disassembly of sources in 3src instructionSagar Ghuge2019-10-211-19/+10
* intel/compiler: Don't move immediate in registerSagar Ghuge2019-10-211-0/+38
* intel/compiler: Set bits according to source fileSagar Ghuge2019-10-211-2/+12
* intel/compiler: Add Immediate support for 3 source instructionSagar Ghuge2019-10-211-21/+32
* intel/compiler: Remove emit_alpha_to_coverage workaround from backendSagar Ghuge2019-10-212-84/+13
* nir: Add alpha_to_coverage lowering passSagar Ghuge2019-10-213-0/+171
* intel/compiler: Report the number of non-spill/fill SEND messagesKenneth Graunke2019-10-171-5/+30
* intel/vec4: Don't try both sources as immediates for DPHIan Romanick2019-10-171-1/+1
* intel/fs/gen12: Add tests for scoreboard passCaio Marcelo de Oliveira Filho2019-10-172-1/+864
* intel/fs/gen12: Use TCS 8_PATCH mode.Kenneth Graunke2019-10-112-6/+8
* intel/fs/gen12: Implement gl_FrontFacing on gen12+.Jason Ekstrand2019-10-112-2/+25
* intel/fs/gen11+: Fix CS_OPCODE_CS_TERMINATE codegen.Francisco Jerez2019-10-112-8/+11
* intel/fs/gen12: Fix barrier codegen.Francisco Jerez2019-10-112-2/+7
* intel/eu: Don't set notify descriptor field of gateway barrier message.Francisco Jerez2019-10-111-1/+0
* intel/ir/gen12: Update assert in brw_stage_has_packed_dispatch().Francisco Jerez2019-10-111-1/+1
* intel/eu/validate/gen12: Don't blow up on indirect src0.Jason Ekstrand2019-10-111-1/+2
* intel/eu/validate/gen12: Validation fixes for SEND instruction.Francisco Jerez2019-10-111-22/+28
* intel/eu/validate/gen12: Fix validation of SYNC instruction.Francisco Jerez2019-10-111-1/+1
* intel/eu/validate/gen12: Implement integer multiply restrictions in EU valida...Francisco Jerez2019-10-111-0/+33
* intel/ir: Lower fpow on Gen12.Jordan Justen2019-10-111-0/+1
* intel/fs/gen12: Don't support source mods for 32x16 integer multiply.Francisco Jerez2019-10-111-0/+18
* intel/disasm: Disassemble register file of split SEND sources.Francisco Jerez2019-10-111-1/+4
* intel/disasm: Don't disassemble saturate control on SEND instructions.Francisco Jerez2019-10-111-2/+4
* intel/disasm/gen12: Disassemble Gen12 SEND instructions.Francisco Jerez2019-10-111-4/+18
* intel/disasm/gen12: Disassemble Gen12 SYNC instruction.Francisco Jerez2019-10-111-0/+14
* intel/disasm/gen12: Disassemble three-source instruction source and destinati...Francisco Jerez2019-10-111-13/+32
* intel/disasm/gen12: Fix disassembly of some common instruction controls.Francisco Jerez2019-10-111-4/+9
* intel/disasm/gen12: Disassemble software scoreboard information.Francisco Jerez2019-10-111-0/+16
* intel/fs/gen12: Demodernize software scoreboard lowering pass.Francisco Jerez2019-10-111-81/+163
* intel/fs/gen12: Introduce software scoreboard lowering pass.Francisco Jerez2019-10-114-0/+945
* intel/fs/gen12: Add scheduling information to the IR.Francisco Jerez2019-10-112-0/+3
* intel/eu/gen12: Set SWSB annotations in hand-crafted assembly.Francisco Jerez2019-10-112-5/+91
* intel/eu/gen12: Add tracking of default SWSB state to the current brw_codegen...Francisco Jerez2019-10-113-0/+18
* intel/eu/gen12: Add auxiliary type to represent SWSB information during codegen.Francisco Jerez2019-10-111-0/+148
* intel/fs/gen12: Add codegen support for the SYNC instruction.Francisco Jerez2019-10-114-3/+19
* intel/ir/gen12: Add SYNC hardware instruction.Francisco Jerez2019-10-113-0/+3
* intel/eu/gen12: Don't set thread control, it's gone.Francisco Jerez2019-10-111-2/+4
* intel/eu/gen12: Don't set DD control, it's gone.Francisco Jerez2019-10-112-6/+12
* intel/eu/gen12: Use SEND instruction for split sends.Francisco Jerez2019-10-112-2/+3
* intel/eu/gen12: Codegen SEND descriptor regions correctly.Francisco Jerez2019-10-112-6/+14
* intel/eu/gen12: Codegen pathological SEND source and destination regions.Francisco Jerez2019-10-111-7/+39
* intel/eu/gen12: Codegen control flow instructions correctly.Francisco Jerez2019-10-111-6/+9
* intel/eu/gen12: Codegen three-source instruction source and destination regions.Francisco Jerez2019-10-112-24/+42
* intel/eu/gen12: Fix codegen of immediate source regions.Francisco Jerez2019-10-111-1/+1
* intel/eu/gen12: Add Gen12 opcode descriptions to the table.Francisco Jerez2019-10-111-24/+47
* intel/eu/gen11+: Mark dot product opcodes as unsupported on opcode_descs table.Francisco Jerez2019-10-111-4/+4
* intel/eu/gen12: Implement datatype binary encoding.Francisco Jerez2019-10-111-7/+55
* intel/eu/gen12: Implement immediate 64 bit constant encoding.Sagar Ghuge2019-10-111-2/+13
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