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* i965/vec4: Relax writemask condition in CSEIan Romanick2018-03-081-1/+9
* i965/fs: Merge CMP and SEL into CSEL on Gen8+Ian Romanick2018-03-082-0/+107
* i965/fs: Add infrastructure for generating CSEL instructions.Kenneth Graunke2018-03-088-1/+34
* anv: Add support for SPIR-V 1.3 subgroup operationsJason Ekstrand2018-03-072-2/+9
* intel/fs: Add support for subgroup quad operationsJason Ekstrand2018-03-075-0/+124
* intel/fs: Implement reduce and scan opeprationsJason Ekstrand2018-03-072-0/+162
* intel/fs: Add a helper for emitting scan operationsJason Ekstrand2018-03-072-0/+148
* intel/fs: Add a couple of simple helper opcodesJason Ekstrand2018-03-074-0/+76
* i965/fs: Add support for nir_intrinsic_shuffleJason Ekstrand2018-03-077-0/+150
* i965/fs: Support nir_intrinsic_vote_feqJason Ekstrand2018-03-071-0/+6
* nir: Generalize nir_intrinsic_vote_eqJason Ekstrand2018-03-071-1/+1
* i965/fs: Implement basic SPIR-V subgroup intrinsicsJason Ekstrand2018-03-072-0/+26
* anv: Trivially implement VK_KHR_device_groupJason Ekstrand2018-03-071-0/+1
* anv: Implement vkCmdDispatchBaseJason Ekstrand2018-03-071-0/+3
* intel: Split gen_device_info out into libintel_devJordan Justen2018-03-053-3/+3
* i965: Silence warnings about mixing enum and non-enum in conditionalIan Romanick2018-03-021-1/+1
* intel/compiler: Silence unused parameter warnings in release buildsIan Romanick2018-03-022-6/+7
* intel: Drop program size pointer from vec4/fs assembly getters.Kenneth Graunke2018-03-029-25/+17
* intel/compiler: Memory fence commit must always be enabled for gen10+Anuj Phogat2018-03-021-1/+3
* Revert "i965/fs: Predicate byte scattered writes if needed"Francisco Jerez2018-03-021-14/+1
* intel/fs: Handle surface opcode sample masks via predication.Francisco Jerez2018-03-021-1/+42
* intel/eu: Plumb header present bit to codegen helpers for HDC messages.Francisco Jerez2018-03-024-29/+50
* intel/ir: Allow arbitrary scratch flag registers for SHADER_OPCODE_FIND_LIVE_...Francisco Jerez2018-03-023-4/+6
* intel/ir: Allow representing additional flag subregisters in the IR.Francisco Jerez2018-03-027-14/+24
* intel/fs: Set up sampler message headers in the visitor on gen7+Jason Ekstrand2018-03-012-22/+39
* spirv/i965/anv: Relax push constant offset assertions being 32-bit alignedJose Maria Casanova Crespo2018-02-281-5/+10
* i965/fs: Support 16-bit store_ssbo with VK_KHR_relaxed_block_layoutJose Maria Casanova Crespo2018-02-281-7/+15
* i965/fs: Support 16-bit do_read_vector with VK_KHR_relaxed_block_layoutJose Maria Casanova Crespo2018-02-281-14/+37
* i965/fs: shuffle_32bit_load_result_to_16bit_data now skips componentsJose Maria Casanova Crespo2018-02-283-3/+6
* isl/i965/fs: SSBO/UBO buffers need size padding if not multiple of 32-bitJose Maria Casanova Crespo2018-02-281-1/+30
* i965: Don't emit MOVs with undefined registers for Gen4 point clipping.Kenneth Graunke2018-02-281-1/+1
* intel/compiler: Re-add .vs_inputs_dual_locations = trueMatt Turner2018-02-281-0/+1
* intel/compiler: Add ICL to test_eu_validate.cppMatt Turner2018-02-281-0/+1
* intel/compiler: Disable Align16 tests on Gen11+Matt Turner2018-02-281-0/+16
* intel/compiler: Add instruction compaction support on Gen11Matt Turner2018-02-281-0/+42
* intel/compiler: Mark line, pln, and lrp as removed on Gen11+Matt Turner2018-02-281-4/+6
* intel/compiler: Lower flrp32 on Gen11+Matt Turner2018-02-285-17/+26
* intel/compiler/fs: Implement ddy without using align16 for Gen11+Matt Turner2018-02-281-8/+38
* intel/compiler/fs: Simplify ddx/ddy code generationMatt Turner2018-02-281-42/+21
* intel/compiler/fs: Pass fs_inst to generate_ddx/ddy instead of opcodeMatt Turner2018-02-282-8/+10
* intel/compiler/fs: Don't generate integer DWord multiply on Gen11Matt Turner2018-02-281-5/+1
* intel/compiler/fs: Implement FS_OPCODE_LINTERP with MADs on Gen11+Matt Turner2018-02-282-4/+46
* intel/compiler/fs: Return multiple_instructions_emitted from generate_linterpMatt Turner2018-02-282-4/+8
* intel/compiler/fs: Fix application of cmod and saturate to LINE/MAC pairMatt Turner2018-02-281-2/+11
* intel/compiler: Add Gen11+ native float typeMatt Turner2018-02-286-2/+32
* intel/compiler: Add Gen11 register typesMatt Turner2018-02-281-8/+65
* nir: add lower_ldexp to nir compiler optionsTimothy Arceri2018-02-281-0/+1
* intel/ir: Fix invalid type aliasing with undefined behavior in test_eu_compact.Francisco Jerez2018-02-271-3/+3
* i965: Fix compiler warning about write being undefined.Eric Anholt2018-02-201-1/+1
* i965/compiler: clean up nir_intrinsic_load_input for vertex shadersIago Toral Quiroga2018-02-141-11/+2
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