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* intel/compiler: move nir_lower_bool_to_int32 before nir_lower_locals_to_regsIago Toral Quiroga2018-12-201-2/+2
* intel/compiler: More peephole_select for pre-Gen6Ian Romanick2018-12-171-2/+2
* nir/opt_peephole_select: Don't peephole_select expensive math instructionsIan Romanick2018-12-171-2/+2
* intel/compiler: More peephole selectIan Romanick2018-12-171-1/+14
* nir/opt_peephole_select: Don't try to remove flow control around indirect loadsIan Romanick2018-12-171-1/+12
* i965/vec4: Propagate conditional modifiers from more compares to other comparesIan Romanick2018-12-171-3/+100
* i965/fs: Eliminate unary op on operand of compare-with-zeroIan Romanick2018-12-172-17/+14
* i965/vec4/dce: Don't narrow the write mask if the flags are usedIan Romanick2018-12-173-10/+203
* i965/vec4: Silence unused parameter warnings in vec4 compiler testsIan Romanick2018-12-173-9/+9
* nir: Add a bool to int32 lowering passJason Ekstrand2018-12-161-0/+2
* nir: Rename Boolean-related opcodes to include 32 in the nameJason Ekstrand2018-12-163-102/+102
* nir: Move intel's half-float image store lowering to to nir_format.h.Eric Anholt2018-12-131-8/+2
* Revert "intel: Simplify the half-float packing in image load/store lowering."Eric Anholt2018-12-131-2/+8
* i965: Enable nir_opt_idiv_const for 32 and 64-bit integersJason Ekstrand2018-12-131-1/+3
* i965/vec4: Implement nir_op_uadd_satJason Ekstrand2018-12-131-0/+6
* i965/fs: Implement nir_op_uadd_satIan Romanick2018-12-131-0/+5
* intel: Simplify the half-float packing in image load/store lowering.Eric Anholt2018-12-121-8/+2
* nir: Pull some of intel's image load/store format conversion to nir_format.hEric Anholt2018-12-121-18/+2
* intel/compiler: do not copy-propagate strided regions to ddx/ddy argumentsIago Toral Quiroga2018-12-121-0/+21
* intel/fs: Support min_lod parameters on texture instructionsJason Ekstrand2018-12-114-2/+31
* intel/ir: Don't allow allocating zero registersJason Ekstrand2018-12-111-0/+1
* i965/fs: Handle V/UV immediates in dump_instructions()Matt Turner2018-12-101-0/+5
* intel/compiler: Always print flag subregister numberSagar Ghuge2018-12-101-7/+6
* intel/compiler: Set swizzle to BRW_SWIZZLE_XXXX for scalar regionSagar Ghuge2018-12-101-1/+18
* nir: Make boolean conversions sized just like the othersJason Ekstrand2018-12-052-11/+17
* mesa: Revert INTEL_fragment_shader_ordering supportMatt Turner2018-12-031-1/+0
* intel/compiler: Use nir's info when checking uses_streams.Kenneth Graunke2018-11-281-1/+1
* intel/compiler: fix register allocation in opt_peephole_selIago Toral Quiroga2018-11-281-2/+1
* intel/compiler: fix indentation style in opt_algebraic()Iago Toral Quiroga2018-11-271-10/+10
* i965: Do NIR shader cloning in the caller.Kenneth Graunke2018-11-206-15/+10
* meson: Add tests to suitesDylan Baker2018-11-201-1/+2
* i965: Allow only one slot of clip distances to be set on Gen4-5.Kenneth Graunke2018-11-191-1/+3
* intel/fs,vec4: Fix a compiler warningJason Ekstrand2018-11-192-3/+3
* intel,nir: Move gl_LocalInvocationID lowering to nir_lower_system_valuesJason Ekstrand2018-11-192-33/+1
* intel/compiler: Lower SSBO and shared loads/stores in NIRJason Ekstrand2018-11-156-405/+420
* intel/compiler: Disassemble GEN6_SFID_DATAPORT_SAMPLER_CACHE as dp_samplerSagar Ghuge2018-11-151-1/+1
* nir: Allow to skip integer ops in nir_lower_to_source_modsGert Wollny2018-11-141-1/+1
* anv/i965: make use of nir_link_constant_varyings()Timothy Arceri2018-11-131-0/+3
* i965: add support for sampling from AYUVLionel Landwerlin2018-11-122-0/+2
* intel/fs: Prevent emission of IR instructions not aligned to their own execut...Francisco Jerez2018-11-091-3/+17
* intel/compiler: fix node interference of simd16 instructionsIago Toral Quiroga2018-11-091-19/+17
* intel/fs: Add an assert to optimize_frontfacing_ternaryJason Ekstrand2018-11-081-0/+3
* intel/analyze_ubo_ranges: Use nir_src_is_const and friendsJason Ekstrand2018-11-081-8/+7
* intel/vec4: Use the new nir_src_is_const and friendsJason Ekstrand2018-11-083-54/+46
* intel/fs: Use the new nir_src_is_const and friendsJason Ekstrand2018-11-081-110/+87
* intel/fs,vec4: Clean up a repeated pattern with SSBOsJason Ekstrand2018-11-084-166/+85
* intel/compiler: Stop assuming the entrypoint is called "main"Jason Ekstrand2018-10-303-22/+5
* intel/nir: Use the OPT macro for more passesJason Ekstrand2018-10-261-3/+3
* nir/builder: Add a nir_imm_true/false helpersJason Ekstrand2018-10-261-1/+1
* nir/validate: Print when the validation failedJason Ekstrand2018-10-261-4/+4
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