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* i965/vec4: split VEC4_OPCODE_FROM_DOUBLE into one opcode per destination's typeSamuel Iglesias Gonsálvez2017-04-147-27/+60
* i965/vec4: split d2x conversion and data gathering from one opcode to two exp...Samuel Iglesias Gonsálvez2017-04-142-8/+1
* i965/vec4: fix VEC4_OPCODE_FROM_DOUBLE for IVB/BYTJuan A. Suarez Romero2017-04-141-7/+19
* i965/vec4: keep original type when dealing with null registersJuan A. Suarez Romero2017-04-141-0/+2
* i965/vec4: split DF instructions and later double its execsize in IVB/BYTSamuel Iglesias Gonsálvez2017-04-143-1/+53
* i965/fs: lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYTSamuel Iglesias Gonsálvez2017-04-141-0/+9
* i965/fs: Get 64-bit indirect moves working on IVB.Francisco Jerez2017-04-141-2/+25
* i965: Use source region <1,2,0> when converting to DF.Matt Turner2017-04-142-13/+28
* i965/fs: fix lower SIMD width for IVB/BYT's MOV_INDIRECTJuan A. Suarez Romero2017-04-141-3/+14
* i965/fs: fix dst stride in IVB/BYT type conversionsJuan A. Suarez Romero2017-04-141-27/+41
* i965/fs: rename lower_d2x to lower_conversionsSamuel Iglesias Gonsálvez2017-04-143-3/+3
* Revert "i965/fs: Don't emit SEL instructions for type-converting MOVs."Samuel Iglesias Gonsálvez2017-04-141-2/+0
* i965/fs: generalize the legalization d2x passSamuel Iglesias Gonsálvez2017-04-142-37/+67
* i965: Use <0,2,1> region for scalar DF sources on IVB/BYT.Matt Turner2017-04-141-0/+13
* i965/fs: clamp exec_size when an instruction has a scalar DF sourceSamuel Iglesias Gonsálvez2017-04-141-3/+8
* i965/fs: double regioning parameters and execsize for DF in IVB/BYTJuan A. Suarez Romero2017-04-141-7/+43
* i965/fs: add helper to retrieve instruction execution typeJuan A. Suarez Romero2017-04-143-5/+64
* i965: Handle IVB DF differences in the validator.Matt Turner2017-04-141-0/+24
* i965/disasm: also print nibctrl in IVB for execsize=8Iago Toral Quiroga2017-04-141-3/+3
* i965/fs: Take into account lower frequency of conditional blocks in spilling ...Francisco Jerez2017-04-111-5/+14
* i965/fs: Always provide a default LOD of 0 for TXS and TXLJason Ekstrand2017-04-041-9/+9
* intel/vec4: Add some fall through commentsJason Ekstrand2017-04-031-0/+4
* i965: expose BRW_OPCODE_[F32TO16/F16TO32] name on gen8+Alejandro Piñeiro2017-03-291-0/+9
* i965/fs: Don't emit SEL instructions for type-converting MOVs.Matt Turner2017-03-271-0/+2
* anv/pipeline: make FragCoord include sample positions when sample shadingIago Toral Quiroga2017-03-241-0/+1
* i965: Replace OPT_V() with OPT().Matt Turner2017-03-231-23/+19
* i965/fs: Return progress from demote_sample_qualifiers().Matt Turner2017-03-231-1/+6
* i965/fs: Return progress from move_interpolation_to_top().Matt Turner2017-03-231-1/+6
* intel/compiler: consistently use ifndef guards over pragma onceEmil Velikov2017-03-228-5/+31
* i965: make brw_setup_image_uniform_values staticEmil Velikov2017-03-221-5/+0
* nir: Rework conversion opcodesJason Ekstrand2017-03-143-67/+45
* i965/fs: Re-arrange conversion operationsJason Ekstrand2017-03-141-36/+31
* i965/vec4: Get rid of the type parameter from to/from_doubleJason Ekstrand2017-03-142-24/+15
* i965/fs: Use num_components from the SSA def in image intrinsicsJason Ekstrand2017-03-141-2/+1
* intel: fix compiler buildIago Toral Quiroga2017-03-131-0/+7
* intel/compiler: whitespace cleanupsEmil Velikov2017-03-132-5/+0
* intel/compiler: link all tests again gtest, even test_eu_compact"Emil Velikov2017-03-131-1/+1
* i965: Move the back-end compiler to src/intel/compilerJason Ekstrand2017-03-1395-0/+63683
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