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* intel/compiler: no need to check unsigned is >= 0Lionel Landwerlin2017-07-131-1/+1
* intel/compiler: don't check unsigned is >= 0Lionel Landwerlin2017-07-131-1/+1
* intel/compiler: remove check unsigned is >= 0Lionel Landwerlin2017-07-131-1/+1
* intel/compiler: Don't use opt_sampler_eot() optimization on gen10+Anuj Phogat2017-07-121-1/+1
* i965/i915: Add UYVY as the supported formatJohnson Lin2017-06-302-0/+2
* intel: compiler/i965: fix is_broxton checksLionel Landwerlin2017-06-203-4/+4
* i965/cnl: Make URB {VS, GS, HS, DS} sizes non multiple of 3Anuj Phogat2017-06-094-4/+33
* i965/cnl: Handle gen10 in switch cases across the driverAnuj Phogat2017-06-092-0/+3
* i965/cnl: Update few assertionsAnuj Phogat2017-06-091-1/+1
* tree-wide: remove trailing backslashEric Engestrom2017-06-071-1/+1
* i965: Change INTEL_DEBUG=vec4 to INTEL_SCALAR_VS for consistency.Kenneth Graunke2017-06-051-1/+1
* i965: Drop duplicate shadow variable.Kenneth Graunke2017-06-011-1/+0
* i965: Move SOL PSIZ hacks from draw time to link time.Kenneth Graunke2017-06-011-12/+1
* i965: Ignore INTEL_SCALAR_* debug variables on Gen10+.Kenneth Graunke2017-05-291-10/+16
* i965: Move clip program compilation to the compilerJason Ekstrand2017-05-268-0/+2340
* i965: Move SF compilation to the compilerJason Ekstrand2017-05-263-0/+931
* intel/compiler: Make brw_disasm take const assemblyJason Ekstrand2017-05-263-15/+15
* i965/vec4: load dvec3/4 uniforms first in the push constant bufferSamuel Iglesias Gonsálvez2017-05-181-27/+80
* i965/vec4: fix swizzle and writemask when loading an uniform with constant of...Samuel Iglesias Gonsálvez2017-05-181-4/+11
* i965/vec4/gs: restore the uniform values which was overwritten by failed vec4...Samuel Iglesias Gonsálvez2017-05-181-0/+26
* i965: Fix test_eu_validate.cppMatt Turner2017-05-161-1/+1
* i965: Add a weak no-op nir_print_instr() symbolMatt Turner2017-05-151-0/+2
* i965: Allow brw_eu_validate to handle compact instructionsMatt Turner2017-05-151-2/+15
* i965: Pass pointer and end of assembly to brw_validate_instructionsMatt Turner2017-05-155-11/+22
* i965/vec4: Delete the system value infastructureJason Ekstrand2017-05-0911-137/+5
* i965/vec4: Use NIR to do GS input remappingJason Ekstrand2017-05-099-101/+59
* i965/fs: Move remapping of gl_PointSize to the NIR levelJason Ekstrand2017-05-092-26/+21
* i965/nir: Inline remap_inputs_with_vue_mapJason Ekstrand2017-05-091-27/+22
* i965/vec4: Use NIR remapping for VS attributesJason Ekstrand2017-05-096-121/+34
* intel/compiler/vs: Move inputs_read handling to generic codeJason Ekstrand2017-05-091-0/+3
* i965/vec4: Set VERT_BIT_EDGEFLAG based on the VUE mapJason Ekstrand2017-05-091-0/+11
* i965/fs: Lower gl_VertexID and friends to inputs at the NIR levelJason Ekstrand2017-05-094-70/+74
* i965/vs: Set uses_vertexid and friends from brw_compile_vsJason Ekstrand2017-05-093-11/+17
* i965: Move multiply by 4 for VS ATTR setup into the scalar backend.Jason Ekstrand2017-05-092-2/+2
* i965/nir: Inline remap_vs_attrsJason Ekstrand2017-05-091-30/+26
* nir: Embed the shader_info in the nir_shader againJason Ekstrand2017-05-0913-132/+132
* intel: compiler: prevent integer overflowLionel Landwerlin2017-05-091-2/+2
* intel: compiler: remove duplicated codeLionel Landwerlin2017-05-091-12/+0
* i965: Move enums to brw_compiler.h.Rafael Antognolli2017-05-032-21/+21
* i965/vec4: don't modify regioning parameters to the sources of DF align1 inst...Samuel Iglesias Gonsálvez2017-05-031-8/+1
* i965/vec4: fix register width for DF VGRF and UNIFORMSamuel Iglesias Gonsálvez2017-05-031-5/+7
* i965/vec4: fix vertical stride to avoid breaking region parameter ruleSamuel Iglesias Gonsálvez2017-05-031-18/+32
* intel/fs: Take into account amount of data read in spilling cost heuristic.Francisco Jerez2017-04-241-1/+1
* intel/fs: Use regs_written() in spilling cost heuristic for improved accuracy.Francisco Jerez2017-04-241-2/+1
* i965/vec4: Use reads_accumulator_implicitly(), not MACH checks.Kenneth Graunke2017-04-241-4/+4
* nir/i965: add before ffma algebraic optsTimothy Arceri2017-04-241-0/+6
* i965/vec4: Avoid reswizzling MACH instructions in opt_register_coalesce().Kenneth Graunke2017-04-221-0/+7
* i965: Use correct VertStride on align16 instructions.Matt Turner2017-04-141-10/+34
* i965/vec4/dce: improve track of partial flag register writesSamuel Iglesias Gonsálvez2017-04-141-1/+1
* i965/vec4: don't do horizontal stride on some register file typesSamuel Iglesias Gonsálvez2017-04-141-2/+5
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