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* intel/compiler/fs: Simplify ddx/ddy code generationMatt Turner2018-02-281-42/+21
* intel/compiler/fs: Pass fs_inst to generate_ddx/ddy instead of opcodeMatt Turner2018-02-282-8/+10
* intel/compiler/fs: Don't generate integer DWord multiply on Gen11Matt Turner2018-02-281-5/+1
* intel/compiler/fs: Implement FS_OPCODE_LINTERP with MADs on Gen11+Matt Turner2018-02-282-4/+46
* intel/compiler/fs: Return multiple_instructions_emitted from generate_linterpMatt Turner2018-02-282-4/+8
* intel/compiler/fs: Fix application of cmod and saturate to LINE/MAC pairMatt Turner2018-02-281-2/+11
* intel/compiler: Add Gen11+ native float typeMatt Turner2018-02-286-2/+32
* intel/compiler: Add Gen11 register typesMatt Turner2018-02-281-8/+65
* nir: add lower_ldexp to nir compiler optionsTimothy Arceri2018-02-281-0/+1
* intel/ir: Fix invalid type aliasing with undefined behavior in test_eu_compact.Francisco Jerez2018-02-271-3/+3
* i965: Fix compiler warning about write being undefined.Eric Anholt2018-02-201-1/+1
* i965/compiler: clean up nir_intrinsic_load_input for vertex shadersIago Toral Quiroga2018-02-141-11/+2
* intel/compiler: fix first_component for 64-bit types on vertex inputsIago Toral Quiroga2018-02-141-0/+3
* intel/compiler: fix 64bit value prints on 32bitGrazvydas Ignotas2018-02-102-3/+3
* i965: remove unused brw_nir_lower_cs_shared()Timothy Arceri2018-02-072-9/+0
* i965/nir: do int64 lowering before optimizationIago Toral Quiroga2018-02-061-4/+12
* i965: Move mistakenly placed lineMatt Turner2018-02-051-1/+1
* nir: add vs_inputs_dual_locations compiler optionTimothy Arceri2018-01-301-0/+3
* compiler: tidy up double_inputs_read usesTimothy Arceri2018-01-301-1/+1
* i965/gen10: Re-enable push constants.Rafael Antognolli2018-01-261-9/+0
* i965/fs: Reset the register file to VGRF in lower_integer_multiplicationJason Ekstrand2018-01-251-5/+10
* i965: Drop render_target_start from binding table struct.Kenneth Graunke2018-01-222-5/+2
* intel/fs: Optimize and simplify the copy propagation dataflow logic.Francisco Jerez2018-01-171-24/+11
* meson: Use dependencies for nirDylan Baker2018-01-111-6/+6
* meson: Use consistent style for testsDylan Baker2018-01-111-8/+11
* meson: Use consistent styleDylan Baker2018-01-111-2/+4
* i965: Use UD types for gl_SampleID setupJason Ekstrand2018-01-111-3/+3
* i965/fs: Use UW types when using V immediatesJason Ekstrand2018-01-112-5/+5
* Revert "Revert "i965/fs: Use align1 mode on ternary instructions on Gen10+""Matt Turner2018-01-111-4/+8
* i965/fs: Add/use functions to convert to 3src_align1 vstride/hstrideMatt Turner2018-01-111-28/+41
* i965/nir: add a helper to lower gl_PatchVerticesIn to a uniformIago Toral Quiroga2018-01-101-0/+2
* i965: Drop support for the legacy SNORM -> Float equation.Kenneth Graunke2018-01-027-41/+13
* i965: Combine {VS,FS}_OPCODE_GET_BUFFER_SIZE opcodes.Kenneth Graunke2017-12-308-19/+14
* Revert "i965/fs: Use align1 mode on ternary instructions on Gen10+"Anuj Phogat2017-12-221-8/+4
* intel/fs: Initialize fs_visitor::grf_used on construction.Francisco Jerez2017-12-211-0/+1
* intel/fs/bank_conflicts: Use posix_memalign() instead of overaligned new to o...Francisco Jerez2017-12-211-6/+16
* intel/compiler/gen10: Disable push constants.Rafael Antognolli2017-12-191-0/+9
* intel/fs/bank_conflicts: Don't touch Gen7 MRF hack registers.Francisco Jerez2017-12-123-7/+19
* i965/fs: Handle !supports_pull_constants and push UBOs properlyJason Ekstrand2017-12-081-1/+1
* i965/fs: Rewrite assign_constant_locationsJason Ekstrand2017-12-081-133/+185
* intel/cfg: Represent divergent control flow paths caused by non-uniform loop ...Francisco Jerez2017-12-071-6/+69
* intel/fs: Don't let undefined values prevent copy propagation.Francisco Jerez2017-12-071-3/+47
* intel/fs: Restrict live intervals to the subset possibly reachable from any d...Francisco Jerez2017-12-072-4/+42
* intel/fs: Teach instruction scheduler about GRF bank conflict cycles.Francisco Jerez2017-12-073-2/+23
* intel/fs: Implement GRF bank conflict mitigation pass.Francisco Jerez2017-12-074-0/+897
* i965/fs: Use untyped_surface_read for 16-bit load_ssboJose Maria Casanova Crespo2017-12-061-7/+20
* i965/fs: Optimize 16-bit SSBO stores by packing two into a 32-bit regJose Maria Casanova Crespo2017-12-061-15/+43
* i965/fs: Enables 16-bit load_ubo with samplerJason Ekstrand2017-12-061-7/+14
* i965/fs: Helpers for un/shuffle 16-bit pairs in 32-bit componentsJose Maria Casanova Crespo2017-12-062-0/+71
* i965/fs: Use byte scattered read for 16-bit load_ssboJose Maria Casanova Crespo2017-12-061-1/+13
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