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* intel/compiler/fs: Switch liveness analysis to IR analysis frameworkFrancisco Jerez2020-03-0612-97/+84
* intel/compiler/vec4: Add live interval validation passFrancisco Jerez2020-03-062-0/+46
* intel/compiler/fs: Add live interval validation passFrancisco Jerez2020-03-062-0/+43
* intel/compiler: Pass single backend_shader argument to the vec4_live_variable...Francisco Jerez2020-03-062-5/+6
* intel/compiler: Pass single backend_shader argument to the fs_live_variables ...Francisco Jerez2020-03-062-11/+10
* intel/compiler: Restructure live intervals computation codeFrancisco Jerez2020-03-062-78/+54
* intel/compiler: Move all live interval analysis results into vec4_live_variablesFrancisco Jerez2020-03-067-25/+36
* intel/compiler: Move all live interval analysis results into fs_live_variablesFrancisco Jerez2020-03-069-42/+43
* intel/compiler: Mark virtual_grf_interferes and vars_interfere as constFrancisco Jerez2020-03-065-6/+6
* intel/compiler: Pass detailed dependency classes to invalidate_analysis()Francisco Jerez2020-03-0620-54/+61
* intel/compiler: Define more detailed analysis dependency classesFrancisco Jerez2020-03-061-0/+46
* intel/compiler: Introduce backend_shader method to propagate IR changes to an...Francisco Jerez2020-03-0624-52/+93
* intel/compiler: Introduce simple IR analysis pass frameworkFrancisco Jerez2020-03-062-0/+147
* intel/compiler: Reverse inclusion dependency between brw_vec4_live_variables....Francisco Jerez2020-03-064-6/+3
* intel/compiler: Reverse inclusion dependency between brw_fs_live_variables.h ...Francisco Jerez2020-03-063-3/+4
* intel/compiler: Nest definition of live variables block_data structuresFrancisco Jerez2020-03-064-82/+83
* intel/compiler: Reverse inclusion dependency between brw_cfg.h and brw_shader.hFrancisco Jerez2020-03-064-6/+6
* intel/compiler: Move base IR definitions into a separate header fileFrancisco Jerez2020-03-063-157/+184
* intel/compiler: Restrict cs_threads to 64Jordan Justen2020-02-281-1/+3
* nir, intel: Move use_scoped_memory_barrier to nir_optionsCaio Marcelo de Oliveira Filho2020-02-241-1/+2
* nir: Move intel's intrinsic_image_coordinate_components() to core nir.Eric Anholt2020-02-241-22/+1
* intel/fs: Correctly handle multiply of fsign with a source modifierIan Romanick2020-02-191-0/+10
* intel/compiler: Do not qsort zero sized arrayDanylo Piliaiev2020-02-191-2/+4
* brw_fs: Avoid zero size vlaDanylo Piliaiev2020-02-191-1/+1
* brw_nir: Cast bitshift to unsignedDanylo Piliaiev2020-02-191-1/+1
* intel/gen12: Take into account opcode when decoding SWSBCaio Marcelo de Oliveira Filho2020-02-182-3/+7
* intel/fs/gen7+: Implement discard/demote for SIMD32 programs.Francisco Jerez2020-02-142-8/+14
* intel/fs: Return consistent UW types from sample_mask_reg() in fragment shaders.Francisco Jerez2020-02-141-3/+2
* intel/fs: Refactor predication on sample mask into helper function.Francisco Jerez2020-02-141-34/+44
* intel/fs/gen7+: Swap sample mask flag register and FIND_LIVE_CHANNEL temporary.Francisco Jerez2020-02-144-13/+18
* intel/fs: Use helper for discard sample mask flag subregister number.Francisco Jerez2020-02-144-5/+16
* intel/fs: Make sample_mask_reg() local to brw_fs.cpp and use it in more places.Francisco Jerez2020-02-142-24/+28
* intel/fs/gen11: Work around dual-source blending hangs in combination with SI...Francisco Jerez2020-02-141-0/+12
* intel/fs: Set src0 alpha present bit in header when provided in message payload.Francisco Jerez2020-02-143-15/+6
* intel/fs/gen12: Workaround data coherency issues due to broken NoMask control...Francisco Jerez2020-02-141-34/+100
* intel/fs/gen12: Fixup/simplify SWSB annotations of SIMD32 scratch writes.Francisco Jerez2020-02-141-7/+3
* intel/fs/gen12: Workaround unwanted SEND execution due to broken NoMask contr...Francisco Jerez2020-02-142-0/+150
* intel/fs: Add virtual instruction to load mask of live channels into flag reg...Francisco Jerez2020-02-145-2/+22
* intel/fs/gen7: Fix fs_inst::flags_written() for SHADER_OPCODE_FIND_LIVE_CHANNEL.Francisco Jerez2020-02-141-1/+2
* intel/fs/cse: Make HALT instruction act as CSE barrier.Francisco Jerez2020-02-141-0/+10
* intel/vec4: fix valgrind errors with vf_values arrayTapani Pälli2020-02-071-1/+2
* glsl,nir: Switch the enum representing shader image formats to PIPE_FORMAT.Eric Anholt2020-02-051-57/+3
* intel/fs: Don't count integer instructions as being possibly coissueIan Romanick2020-02-051-1/+8
* intel/fs: Write the address register with NoMask for MOV_INDIRECTJason Ekstrand2020-01-311-0/+9
* intel/disasm: SEND has two sources on Gen12+Jason Ekstrand2020-01-311-2/+4
* intel/eu/validate: Don't validate regions of sendsJason Ekstrand2020-01-311-3/+3
* intel/compiler: Clear accumulator register before EOTSagar Ghuge2020-01-271-0/+18
* intel: Implement Gen12 workaround for array textures of size 1Lionel Landwerlin2020-01-264-0/+145
* intel/compiler: Add names for SHADER_OPCODE_[IU]SUB_SATCaio Marcelo de Oliveira Filho2020-01-241-0/+4
* intel/disasm: Properly disassemble indirect SENDsJason Ekstrand2020-01-241-3/+16
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