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path: root/src/intel/compiler/brw_vec4_nir.cpp
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* intel/compiler: Delete abs/neg handling in fsign codeKenneth Graunke2020-04-221-13/+1
* intel/compiler: Drop nir_lower_to_source_mods() and related handling.Kenneth Graunke2020-04-211-51/+15
* nir: Delete the fnoise opcodesJason Ekstrand2020-04-211-18/+0
* intel/vec4: fix valgrind errors with vf_values arrayTapani Pälli2020-02-071-1/+2
* intel/compiler: Move Gen4/5 rounding to visitorMatt Turner2020-01-221-0/+12
* intel/vec4: Support scoped_memory_barrierJason Ekstrand2020-01-131-1/+2
* intel/vec4: Fix lowering of multiplication by 16-bit constantCaio Marcelo de Oliveira Filho2019-12-171-2/+14
* intel/vec4: Set brw_stage_prog_data::has_ubo_pullJason Ekstrand2019-10-301-0/+2
* intel/vec4: Don't try both sources as immediates for DPHIan Romanick2019-10-171-1/+1
* intel/compiler: Silence maybe-uninitialized warning in GCC 9.1.1Caio Marcelo de Oliveira Filho2019-08-231-1/+3
* intel/nir: Add a helper for getting BRW_AOP from an intrinsicJason Ekstrand2019-08-211-31/+2
* intel/nir: Add a common nir comparison -> cmod helperJason Ekstrand2019-08-031-43/+4
* intel/vec4: Drop all of the 64-bit varying codeJason Ekstrand2019-07-311-37/+7
* tree-wide: replace MAYBE_UNUSED with ASSERTEDEric Engestrom2019-07-311-1/+1
* intel/vec4: Try to emit immediate sources for MOVIan Romanick2019-07-111-4/+14
* intel/vec4: Try to emit a VF source in try_immediate_sourceIan Romanick2019-07-111-12/+33
* intel/vec4: Try to emit a single load for multiple 3-src instruction operandsIan Romanick2019-07-111-3/+35
* intel/vec4: Refactor operand fixing for ffma and flrpIan Romanick2019-07-111-8/+13
* intel/vec4: Delete vec4_visitor::emit_lrpIan Romanick2019-07-081-1/+5
* intel/vec4: Try both sources as candidates for being immediatesIan Romanick2019-06-281-41/+80
* intel/vec4: Try immediate sources for dot products tooIan Romanick2019-06-281-0/+4
* intel/vec4: Try emitting non-scalar immediatesIan Romanick2019-06-281-4/+31
* intel/fs,vec4: Use g0 as the header for MFENCEJason Ekstrand2019-05-301-1/+1
* nir: Drop imov/fmov in favor of one mov instructionJason Ekstrand2019-05-241-2/+1
* intel: Implement abs, neg, and sat in the back-endJason Ekstrand2019-05-241-9/+22
* nir: make nir_const_value scalarKarol Herbst2019-04-141-4/+4
* intel/nir: Take a nir_tex_instr and src index in brw_texture_offsetJason Ekstrand2019-04-141-9/+2
* spirv: Use the same types for resource indices as pointersJason Ekstrand2019-03-051-0/+1
* intel/vec4: Emit constants for some ALU sources as immediate valuesIan Romanick2019-03-011-0/+71
* intel: Use the NIR lowering for isign.Eric Anholt2019-02-141-12/+0
* i965: Drop mark_surface_used mechanism.Kenneth Graunke2019-01-131-29/+0
* nir: Rename Boolean-related opcodes to include 32 in the nameJason Ekstrand2018-12-161-57/+57
* i965/vec4: Implement nir_op_uadd_satJason Ekstrand2018-12-131-0/+6
* nir: Make boolean conversions sized just like the othersJason Ekstrand2018-12-051-4/+5
* intel/fs,vec4: Fix a compiler warningJason Ekstrand2018-11-191-1/+1
* intel/compiler: Lower SSBO and shared loads/stores in NIRJason Ekstrand2018-11-151-112/+14
* intel/vec4: Use the new nir_src_is_const and friendsJason Ekstrand2018-11-081-44/+38
* intel/fs,vec4: Clean up a repeated pattern with SSBOsJason Ekstrand2018-11-081-79/+45
* intel/compiler: Stop assuming the entrypoint is called "main"Jason Ekstrand2018-10-301-6/+1
* intel/vec4: Fix nir_op_b2[fi] with 64-bit resultJason Ekstrand2018-10-111-1/+6
* intel/compiler: Don't handle fsign.satIan Romanick2018-10-091-10/+2
* i965/vec4: Emit BRW_AOP_INC or BRW_AOP_DEC for atomicAdd of +1 or -1Ian Romanick2018-08-281-3/+16
* i965/vec4: Properly handle sign(-abs(x))Ian Romanick2018-07-061-1/+17
* i965/vec4: Make the vec4_visitor::nir_emit_instr default case unreachableIan Romanick2018-07-051-2/+1
* i965: Combine {VS,FS}_OPCODE_GET_BUFFER_SIZE opcodes.Kenneth Graunke2017-12-301-1/+1
* i965/vec4: use a temp register to compute offsets for pull loadsIago Toral Quiroga2017-11-301-1/+3
* i965: Use nir_lower_atomics_to_ssbos and delete ABO compiler code.Kenneth Graunke2017-11-151-46/+0
* i965/vec4: remove setting default LOD in the backendSamuel Iglesias Gonsálvez2017-10-201-9/+0
* intel: compiler: vec4: add missing default 0 lodLionel Landwerlin2017-10-031-0/+9
* i965/vec4: Actually handle atomic op intrinsics.Kenneth Graunke2017-09-261-2/+10
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