summaryrefslogtreecommitdiffstats
path: root/src/intel/compiler/brw_vec4_nir.cpp
Commit message (Expand)AuthorAgeFilesLines
* intel/fs,vec4: Use g0 as the header for MFENCEJason Ekstrand2019-05-301-1/+1
* nir: Drop imov/fmov in favor of one mov instructionJason Ekstrand2019-05-241-2/+1
* intel: Implement abs, neg, and sat in the back-endJason Ekstrand2019-05-241-9/+22
* nir: make nir_const_value scalarKarol Herbst2019-04-141-4/+4
* intel/nir: Take a nir_tex_instr and src index in brw_texture_offsetJason Ekstrand2019-04-141-9/+2
* spirv: Use the same types for resource indices as pointersJason Ekstrand2019-03-051-0/+1
* intel/vec4: Emit constants for some ALU sources as immediate valuesIan Romanick2019-03-011-0/+71
* intel: Use the NIR lowering for isign.Eric Anholt2019-02-141-12/+0
* i965: Drop mark_surface_used mechanism.Kenneth Graunke2019-01-131-29/+0
* nir: Rename Boolean-related opcodes to include 32 in the nameJason Ekstrand2018-12-161-57/+57
* i965/vec4: Implement nir_op_uadd_satJason Ekstrand2018-12-131-0/+6
* nir: Make boolean conversions sized just like the othersJason Ekstrand2018-12-051-4/+5
* intel/fs,vec4: Fix a compiler warningJason Ekstrand2018-11-191-1/+1
* intel/compiler: Lower SSBO and shared loads/stores in NIRJason Ekstrand2018-11-151-112/+14
* intel/vec4: Use the new nir_src_is_const and friendsJason Ekstrand2018-11-081-44/+38
* intel/fs,vec4: Clean up a repeated pattern with SSBOsJason Ekstrand2018-11-081-79/+45
* intel/compiler: Stop assuming the entrypoint is called "main"Jason Ekstrand2018-10-301-6/+1
* intel/vec4: Fix nir_op_b2[fi] with 64-bit resultJason Ekstrand2018-10-111-1/+6
* intel/compiler: Don't handle fsign.satIan Romanick2018-10-091-10/+2
* i965/vec4: Emit BRW_AOP_INC or BRW_AOP_DEC for atomicAdd of +1 or -1Ian Romanick2018-08-281-3/+16
* i965/vec4: Properly handle sign(-abs(x))Ian Romanick2018-07-061-1/+17
* i965/vec4: Make the vec4_visitor::nir_emit_instr default case unreachableIan Romanick2018-07-051-2/+1
* i965: Combine {VS,FS}_OPCODE_GET_BUFFER_SIZE opcodes.Kenneth Graunke2017-12-301-1/+1
* i965/vec4: use a temp register to compute offsets for pull loadsIago Toral Quiroga2017-11-301-1/+3
* i965: Use nir_lower_atomics_to_ssbos and delete ABO compiler code.Kenneth Graunke2017-11-151-46/+0
* i965/vec4: remove setting default LOD in the backendSamuel Iglesias Gonsálvez2017-10-201-9/+0
* intel: compiler: vec4: add missing default 0 lodLionel Landwerlin2017-10-031-0/+9
* i965/vec4: Actually handle atomic op intrinsics.Kenneth Graunke2017-09-261-2/+10
* i965: Mark functions staticMatt Turner2017-08-211-2/+3
* i965/vec4: fix swizzle and writemask when loading an uniform with constant of...Samuel Iglesias Gonsálvez2017-05-181-4/+11
* i965/vec4: Delete the system value infastructureJason Ekstrand2017-05-091-38/+0
* i965/vec4: Use NIR remapping for VS attributesJason Ekstrand2017-05-091-47/+2
* nir: Embed the shader_info in the nir_shader againJason Ekstrand2017-05-091-4/+4
* i965/vec4: use vec4_builder to emit instructions in setup_imm_df()Samuel Iglesias Gonsálvez2017-04-141-48/+49
* i965/vec4: split VEC4_OPCODE_FROM_DOUBLE into one opcode per destination's typeSamuel Iglesias Gonsálvez2017-04-141-6/+18
* i965/vec4: split d2x conversion and data gathering from one opcode to two exp...Samuel Iglesias Gonsálvez2017-04-141-0/+1
* intel/vec4: Add some fall through commentsJason Ekstrand2017-04-031-0/+4
* nir: Rework conversion opcodesJason Ekstrand2017-03-141-38/+29
* i965/vec4: Get rid of the type parameter from to/from_doubleJason Ekstrand2017-03-141-20/+13
* i965: Move the back-end compiler to src/intel/compilerJason Ekstrand2017-03-131-0/+2407
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-24 20:09:26 +0000