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path: root/src/intel/compiler/brw_vec4_generator.cpp
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* intel/compiler: Fill a compiler statistics structJason Ekstrand2019-08-121-4/+13
* intel/compiler: add ability to override shader's assemblyDanylo Piliaiev2019-08-051-9/+22
* intel/fs: Add support for SLM fence in Gen11Caio Marcelo de Oliveira Filho2019-07-111-1/+1
* intel/fs: Do a stalling MFENCE in endInvocationInterlock()Jason Ekstrand2019-05-301-1/+1
* intel/fs,vec4: Use g0 as the header for MFENCEJason Ekstrand2019-05-301-1/+1
* intel/compiler: Replicate 16 bit immediate value correctlySagar Ghuge2019-05-071-0/+3
* intel/common: move gen_debug to intel/devMark Janes2019-04-101-1/+1
* intel/compiler: Re-prefix non-logical surface opcodes with VEC4Jason Ekstrand2019-02-281-3/+3
* intel/vec4: Drop dead code for handling typed surface messagesJason Ekstrand2019-02-281-18/+0
* intel/eu: Add an EOT parameter to send_indirect_[split]_messageJason Ekstrand2019-02-251-2/+4
* i965: Drop mark_surface_used mechanism.Kenneth Graunke2019-01-131-9/+0
* i965/vec4: Correctly handle uniform sources in generate_tes_add_indirect_urb_...Ian Romanick2018-09-011-1/+14
* intel/eu: Use descriptor constructors for dataport write messages.Francisco Jerez2018-07-091-12/+10
* intel/eu: Use descriptor constructors for dataport read messages.Francisco Jerez2018-07-091-17/+16
* intel/eu: Use descriptor constructors for sampler messages.Francisco Jerez2018-07-091-32/+27
* intel/eu: Provide desc immediate argument up front to brw_send_indirect_messa...Francisco Jerez2018-07-091-2/+2
* intel/eu: Use brw_set_desc() along with a helper to set common descriptor con...Francisco Jerez2018-07-091-9/+8
* i965: Add ARB_fragment_shader_interlock support.Plamena Manolova2018-06-011-1/+1
* intel/compiler: Silence unused parameter warnings in generate_foo methodsIan Romanick2018-04-241-4/+4
* intel: Drop program size pointer from vec4/fs assembly getters.Kenneth Graunke2018-03-021-3/+2
* intel/eu: Plumb header present bit to codegen helpers for HDC messages.Francisco Jerez2018-03-021-5/+6
* intel/ir: Allow representing additional flag subregisters in the IR.Francisco Jerez2018-03-021-1/+1
* i965: Combine {VS,FS}_OPCODE_GET_BUFFER_SIZE opcodes.Kenneth Graunke2017-12-301-5/+4
* intel: fix disasm_info memory leaksTapani Pälli2017-11-211-1/+1
* i965: Rewrite disassembly annotation codeMatt Turner2017-11-171-9/+9
* i965: Move common code out of #ifdefMatt Turner2017-11-171-4/+2
* nir: Get rid of nir_shader::stageJason Ekstrand2017-10-201-5/+5
* i965: Normalize types for FBL, FBH, etcMatt Turner2017-09-301-7/+5
* i965: Pass pointer and end of assembly to brw_validate_instructionsMatt Turner2017-05-151-2/+6
* nir: Embed the shader_info in the nir_shader againJason Ekstrand2017-05-091-2/+2
* i965/vec4: don't modify regioning parameters to the sources of DF align1 inst...Samuel Iglesias Gonsálvez2017-05-031-8/+1
* i965/vec4: Fix exec size for MOVs {SET,PICK}_{HIGH,LOW}_32BIT.Matt Turner2017-04-141-4/+12
* i965/vec4: fix assert to detect SIMD lowered DF instructions in IVBFrancisco Jerez2017-04-141-5/+1
* i965/vec4: split VEC4_OPCODE_FROM_DOUBLE into one opcode per destination's typeSamuel Iglesias Gonsálvez2017-04-141-2/+21
* i965/vec4: split d2x conversion and data gathering from one opcode to two exp...Samuel Iglesias Gonsálvez2017-04-141-8/+0
* i965/vec4: fix VEC4_OPCODE_FROM_DOUBLE for IVB/BYTJuan A. Suarez Romero2017-04-141-7/+19
* i965/vec4: split DF instructions and later double its execsize in IVB/BYTSamuel Iglesias Gonsálvez2017-04-141-1/+10
* i965: Use source region <1,2,0> when converting to DF.Matt Turner2017-04-141-12/+1
* i965: Move the back-end compiler to src/intel/compilerJason Ekstrand2017-03-131-0/+2217
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