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path: root/src/intel/compiler/brw_vec4.cpp
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* i965/cnl: Make URB {VS, GS, HS, DS} sizes non multiple of 3Anuj Phogat2017-06-091-2/+9
* i965/vec4: load dvec3/4 uniforms first in the push constant bufferSamuel Iglesias Gonsálvez2017-05-181-27/+80
* i965/vec4: Use NIR to do GS input remappingJason Ekstrand2017-05-091-60/+0
* i965/vec4: Use NIR remapping for VS attributesJason Ekstrand2017-05-091-36/+24
* intel/compiler/vs: Move inputs_read handling to generic codeJason Ekstrand2017-05-091-0/+3
* i965/vec4: Set VERT_BIT_EDGEFLAG based on the VUE mapJason Ekstrand2017-05-091-0/+11
* i965/vs: Set uses_vertexid and friends from brw_compile_vsJason Ekstrand2017-05-091-0/+17
* nir: Embed the shader_info in the nir_shader againJason Ekstrand2017-05-091-10/+10
* i965/vec4: fix register width for DF VGRF and UNIFORMSamuel Iglesias Gonsálvez2017-05-031-5/+7
* i965/vec4: fix vertical stride to avoid breaking region parameter ruleSamuel Iglesias Gonsálvez2017-05-031-18/+32
* i965/vec4: Use reads_accumulator_implicitly(), not MACH checks.Kenneth Graunke2017-04-241-4/+4
* i965/vec4: Avoid reswizzling MACH instructions in opt_register_coalesce().Kenneth Graunke2017-04-221-0/+7
* i965/vec4: split VEC4_OPCODE_FROM_DOUBLE into one opcode per destination's typeSamuel Iglesias Gonsálvez2017-04-141-3/+9
* i965/vec4: keep original type when dealing with null registersJuan A. Suarez Romero2017-04-141-0/+2
* i965/vec4: split DF instructions and later double its execsize in IVB/BYTSamuel Iglesias Gonsálvez2017-04-141-0/+10
* i965: Move the back-end compiler to src/intel/compilerJason Ekstrand2017-03-131-0/+2851
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