| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | i965/vec4: fix register width for DF VGRF and UNIFORM | Samuel Iglesias Gonsálvez | 2017-05-03 | 1 | -5/+7 |
| * | i965/vec4: fix vertical stride to avoid breaking region parameter rule | Samuel Iglesias Gonsálvez | 2017-05-03 | 1 | -18/+32 |
| * | i965/vec4: Use reads_accumulator_implicitly(), not MACH checks. | Kenneth Graunke | 2017-04-24 | 1 | -4/+4 |
| * | i965/vec4: Avoid reswizzling MACH instructions in opt_register_coalesce(). | Kenneth Graunke | 2017-04-22 | 1 | -0/+7 |
| * | i965/vec4: split VEC4_OPCODE_FROM_DOUBLE into one opcode per destination's type | Samuel Iglesias Gonsálvez | 2017-04-14 | 1 | -3/+9 |
| * | i965/vec4: keep original type when dealing with null registers | Juan A. Suarez Romero | 2017-04-14 | 1 | -0/+2 |
| * | i965/vec4: split DF instructions and later double its execsize in IVB/BYT | Samuel Iglesias Gonsálvez | 2017-04-14 | 1 | -0/+10 |
| * | i965: Move the back-end compiler to src/intel/compiler | Jason Ekstrand | 2017-03-13 | 1 | -0/+2851 |
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