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path: root/src/intel/compiler/brw_nir.c
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* nir: Use the flrp lowering pass instead of nir_opt_algebraicIan Romanick2019-05-061-0/+23
* intel/fs: Don't handle texop_tex for shaders without implicit LODCaio Marcelo de Oliveira Filho2019-04-251-0/+1
* intel,nir: Lower TXD with a bindless samplerJason Ekstrand2019-04-191-0/+1
* intel/nir: Re-run int64 lowering in postprocess_nirJason Ekstrand2019-04-191-0/+1
* intel/compiler: activate 16-bit bit-size lowerings also for 8-bitIago Toral Quiroga2019-04-181-1/+1
* intel/compiler: handle extended math restrictions for half-floatIago Toral Quiroga2019-04-181-1/+12
* intel/compiler: lower some 16-bit float operations to 32-bitIago Toral Quiroga2019-04-181-0/+5
* intel/compiler: add a NIR pass to lower conversionsIago Toral Quiroga2019-04-181-0/+2
* intel/nir: use nir_src_is_const and nir_src_as_uintKarol Herbst2019-04-141-6/+4
* intel/common: move gen_debug to intel/devMark Janes2019-04-101-1/+1
* nir/radv: remove restrictions on opt_if_loop_last_continue()Timothy Arceri2019-04-091-1/+1
* intel/compiler: Use partial redundancy elimination for comparesIan Romanick2019-03-281-0/+20
* anv,radv,turnip: Lower TG4 offsets with nir_lower_texJason Ekstrand2019-03-211-0/+1
* intel/nir: Lower array-deref-of-vector UBO and SSBO loadsJason Ekstrand2019-03-151-0/+11
* intel/nir: Combine store_derefs to improve code from SPIR-VCaio Marcelo de Oliveira Filho2019-03-131-0/+1
* intel/nir: Combine store_derefs after vectorizing IOCaio Marcelo de Oliveira Filho2019-03-131-0/+1
* nir: Add a pass to combine store_derefs to same vectorCaio Marcelo de Oliveira Filho2019-03-131-0/+1
* intel/nir: Vectorize all IOJason Ekstrand2019-03-121-0/+17
* intel/nir: Move lower_mem_access_bit_sizes to postprocess_nirJason Ekstrand2019-03-081-2/+1
* intel/nir: Move 64-bit lowering laterJason Ekstrand2019-03-061-21/+13
* nir/lower_doubles: Inline functions directly in lower_doublesJason Ekstrand2019-03-061-18/+4
* intel/nir: Drop an unneeded lower_constant_initializers callJason Ekstrand2019-03-061-2/+0
* intel,nir: Lower TXD with min_lod when the sampler index is not < 16Jason Ekstrand2019-03-041-1/+3
* intel/compiler: Move int64/doubles lowering optionsJordan Justen2019-03-021-30/+2
* i965: Add support for sampling from XYUV imagesKasireddy, Vivek2019-02-261-0/+1
* intel/compiler: add scale_factors to sampler_prog_key_dataTapani Pälli2019-02-121-0/+4
* nir: replace more nir_load_system_value calls with builder functionsKarol Herbst2019-01-211-2/+1
* nir: rename nir_var_function to nir_var_function_tempKarol Herbst2019-01-191-7/+7
* intel/nir: Call nir_opt_deref in brw_nir_optimizeJason Ekstrand2019-01-121-0/+1
* i965: Compile fp64 software routines and lower double-opsMatt Turner2019-01-091-22/+70
* nir: rename global/local to private/function memoryKarol Herbst2019-01-081-5/+5
* nir: rename nir_link_constant_varyings() nir_link_opt_varyings()Timothy Arceri2019-01-021-1/+1
* intel/compiler: move nir_lower_bool_to_int32 before nir_lower_locals_to_regsIago Toral Quiroga2018-12-201-2/+2
* intel/compiler: More peephole_select for pre-Gen6Ian Romanick2018-12-171-2/+2
* nir/opt_peephole_select: Don't peephole_select expensive math instructionsIan Romanick2018-12-171-2/+2
* intel/compiler: More peephole selectIan Romanick2018-12-171-1/+14
* nir/opt_peephole_select: Don't try to remove flow control around indirect loadsIan Romanick2018-12-171-1/+12
* nir: Add a bool to int32 lowering passJason Ekstrand2018-12-161-0/+2
* i965: Enable nir_opt_idiv_const for 32 and 64-bit integersJason Ekstrand2018-12-131-1/+3
* intel/fs: Support min_lod parameters on texture instructionsJason Ekstrand2018-12-111-0/+3
* intel/compiler: Lower SSBO and shared loads/stores in NIRJason Ekstrand2018-11-151-0/+2
* nir: Allow to skip integer ops in nir_lower_to_source_modsGert Wollny2018-11-141-1/+1
* anv/i965: make use of nir_link_constant_varyings()Timothy Arceri2018-11-131-0/+3
* i965: add support for sampling from AYUVLionel Landwerlin2018-11-121-0/+1
* intel/nir: Use the OPT macro for more passesJason Ekstrand2018-10-261-3/+3
* nir/validate: Print when the validation failedJason Ekstrand2018-10-261-4/+4
* intel/nir, freedreno/ir3: Use the separated dead write vars passCaio Marcelo de Oliveira Filho2018-10-151-0/+1
* intel/compiler: Export TCS passthrough creationCaio Marcelo de Oliveira Filho2018-09-251-0/+81
* Replace uses of _mesa_bitcount with util_bitcountDylan Baker2018-09-071-2/+3
* intel/compiler: Remove redundant nir_remove_dead_variables callJason Ekstrand2018-09-041-2/+0
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