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path: root/src/intel/compiler/brw_nir.c
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* intel/nir: Run copy-prop and DCE after lower_bool_to_int32Jason Ekstrand2020-03-301-0/+2
* intel/fs: Combine adjacent memory barriersCaio Marcelo de Oliveira Filho2020-03-121-0/+22
* brw_nir: Cast bitshift to unsignedDanylo Piliaiev2020-02-191-1/+1
* intel: Implement Gen12 workaround for array textures of size 1Lionel Landwerlin2020-01-261-0/+3
* anv,nir: Lower quad_broadcast with dynamic index in NIRJason Ekstrand2020-01-151-0/+1
* nir/lower_gs_intrinsics: add option for per-stream countsRhys Perry2020-01-141-1/+1
* intel/compiler: Increase nir_opt_peephole_select thresholdIan Romanick2019-12-021-1/+1
* intel/fs: Do not lower large local arrays to scratch on gen7Danylo Piliaiev2019-11-141-1/+5
* intel/fs: Lower large local arrays to scratchJason Ekstrand2019-11-111-0/+19
* intel/nir: Plumb devinfo through lower_mem_access_bit_sizesJason Ekstrand2019-11-111-1/+1
* nir/large_constants: pass after lowering copy_derefSergii Romantsov2019-09-161-7/+7
* nir: allow specifying filter callback in lower_alu_to_scalarVasily Khoruzhick2019-09-061-3/+3
* intel/nir: Add a helper for getting BRW_AOP from an intrinsicJason Ekstrand2019-08-211-0/+66
* nir: merge and extend nir_opt_move_comparisons and nir_opt_move_load_uboRhys Perry2019-08-121-1/+1
* intel/nir: Add 1-bit opcodes to brw_cmod_for_nir_comparison_opJason Ekstrand2019-08-031-0/+10
* intel/nir: Add a common nir comparison -> cmod helperJason Ekstrand2019-08-031-0/+39
* intel: Use NIR to lower 64-bit varying accessJason Ekstrand2019-07-311-6/+11
* intel/compiler: Allow for required subgroup sizesJason Ekstrand2019-07-241-0/+9
* intel/compiler: Allow for varying subgroup sizesJason Ekstrand2019-07-241-2/+17
* intel/compiler: Be more conservative about subgroup sizes in GLJason Ekstrand2019-07-241-7/+32
* intel/compiler: Lower gl_SubgroupSize in postprocess_nirJason Ekstrand2019-07-241-2/+7
* intel/nir: Make brw_nir_apply_sampler_key more genericJason Ekstrand2019-07-241-6/+16
* intel/compiler: Use nir_opt_conditional_discardCaio Marcelo de Oliveira Filho2019-07-221-0/+1
* st,i965: Stop looping on 64-bit loweringJason Ekstrand2019-07-161-12/+2
* intel: Run the optimization loop before and after lowering int64Jason Ekstrand2019-07-131-1/+3
* intel/compiler: remove abandoned commentsAndres Gomez2019-07-121-3/+0
* intel/nir: Extract add_const_offset_to_baseConnor Abbott2019-07-081-74/+23
* intel/fs: Use nir_lower_interpolation on gen11+Jason Ekstrand2019-07-021-0/+2
* intel/fs: Implement nir_intrinsic_load_fs_input_interp_deltasJason Ekstrand2019-07-021-1/+2
* intel/nir: Take nir_shader*s in brw_nir_link_shadersJason Ekstrand2019-06-051-34/+32
* intel/nir: Stop returning the shader from helpersJason Ekstrand2019-06-051-22/+14
* intel/compiler: Use compare rematerialization passIan Romanick2019-05-311-0/+3
* intel/nir: Call alu_to_scalar one last time before out-of-ssaJason Ekstrand2019-05-241-0/+2
* intel/compiler: Repeat nir_opt_algebraic_lateIan Romanick2019-05-141-1/+16
* nir: allow specifying a set of opcodes in lower_alu_to_scalarJonathan Marek2019-05-101-2/+2
* intel/compiler: Don't always require precise lowering of flrpIan Romanick2019-05-061-1/+1
* nir: Use the flrp lowering pass instead of nir_opt_algebraicIan Romanick2019-05-061-0/+23
* intel/fs: Don't handle texop_tex for shaders without implicit LODCaio Marcelo de Oliveira Filho2019-04-251-0/+1
* intel,nir: Lower TXD with a bindless samplerJason Ekstrand2019-04-191-0/+1
* intel/nir: Re-run int64 lowering in postprocess_nirJason Ekstrand2019-04-191-0/+1
* intel/compiler: activate 16-bit bit-size lowerings also for 8-bitIago Toral Quiroga2019-04-181-1/+1
* intel/compiler: handle extended math restrictions for half-floatIago Toral Quiroga2019-04-181-1/+12
* intel/compiler: lower some 16-bit float operations to 32-bitIago Toral Quiroga2019-04-181-0/+5
* intel/compiler: add a NIR pass to lower conversionsIago Toral Quiroga2019-04-181-0/+2
* intel/nir: use nir_src_is_const and nir_src_as_uintKarol Herbst2019-04-141-6/+4
* intel/common: move gen_debug to intel/devMark Janes2019-04-101-1/+1
* nir/radv: remove restrictions on opt_if_loop_last_continue()Timothy Arceri2019-04-091-1/+1
* intel/compiler: Use partial redundancy elimination for comparesIan Romanick2019-03-281-0/+20
* anv,radv,turnip: Lower TG4 offsets with nir_lower_texJason Ekstrand2019-03-211-0/+1
* intel/nir: Lower array-deref-of-vector UBO and SSBO loadsJason Ekstrand2019-03-151-0/+11
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