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path: root/src/intel/compiler/brw_fs_nir.cpp
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* nir,intel/compiler: Use a fixed subgroup sizeJason Ekstrand2017-11-071-4/+0
* intel/fs: Explicitly set EXECUTE_1 where neededJason Ekstrand2017-11-071-4/+4
* intel/compiler/fs: Set up subgroup invocation as a system valueJason Ekstrand2017-11-071-13/+21
* intel/cs: Push subgroup ID instead of base thread IDJason Ekstrand2017-11-071-4/+4
* intel/cs: Rework the way thread local ID is handledJason Ekstrand2017-11-071-0/+14
* intel/fs: use pull constant locations to check for first compile of a shaderJason Ekstrand2017-11-071-1/+4
* intel/fs: Retype dest to match value in read[First]InvocationJason Ekstrand2017-11-071-4/+2
* intel/fs: Uniformize the index in readInvocationJason Ekstrand2017-11-071-1/+1
* i965/fs/nir: Don't stomp 64-bit values to D in get_nir_srcJason Ekstrand2017-11-071-13/+24
* i965/fs/nir: Minor refactor of store_outputJason Ekstrand2017-11-071-4/+3
* i965/fs: Return a fs_reg from shuffle_64bit_data_for_32bit_writeJason Ekstrand2017-11-071-25/+9
* i965/fs/nir: Simplify 64-bit store_outputJason Ekstrand2017-11-071-19/+6
* intel/fs: Use a pair of 1-wide MOVs instead of SEL for any/allJason Ekstrand2017-11-071-9/+33
* intel/fs: Use an explicit D type for vote any/all/eq intrinsicsJason Ekstrand2017-11-071-0/+6
* intel/fs: Don't stomp f0.1 in SIMD16 ballotJason Ekstrand2017-11-071-2/+9
* intel/fs: Use ANY/ALL32 predicates in SIMD32Jason Ekstrand2017-11-071-12/+30
* i965/fs: Add brw_reg_type_from_bit_size utility methodAlejandro Piñeiro2017-10-251-5/+64
* i965/fs/nir: Use the nir_src_bit_size helperJason Ekstrand2017-10-251-9/+3
* i965/fs: remove setting default LOD in the backendSamuel Iglesias Gonsálvez2017-10-201-9/+0
* i965: Fix output register sizes when multiple variables share a slot.Kenneth Graunke2017-10-101-5/+18
* i965/tes: account for the fact that dvec3/4 inputs take two slotsIago Toral Quiroga2017-10-101-2/+7
* i965/fs: Rewrite fsign64 to skip the float -> double conversionMatt Turner2017-10-041-41/+9
* i965/fs: Unpack count argument to 64-bit shift ops on AtomMatt Turner2017-10-041-6/+28
* i965/fs: force pull model for 64-bit GS inputsIago Toral Quiroga2017-09-291-1/+3
* i965/fs: Match destination type to size for ballotMatt Turner2017-07-201-1/+5
* i965/fs: Implement ARB_shader_ballot operationsMatt Turner2017-07-201-0/+46
* nir: Add system values from ARB_shader_ballotMatt Turner2017-07-201-1/+1
* i965/fs: Implement ARB_shader_group_vote operationsMatt Turner2017-07-201-0/+50
* i965: Use pushed UBO data in the scalar backend.Kenneth Graunke2017-07-131-0/+28
* intel/compiler: no need to check unsigned is >= 0Lionel Landwerlin2017-07-131-1/+1
* intel: compiler/i965: fix is_broxton checksLionel Landwerlin2017-06-201-2/+2
* i965/fs: Move remapping of gl_PointSize to the NIR levelJason Ekstrand2017-05-091-23/+3
* i965/fs: Lower gl_VertexID and friends to inputs at the NIR levelJason Ekstrand2017-05-091-29/+1
* i965: Move multiply by 4 for VS ATTR setup into the scalar backend.Jason Ekstrand2017-05-091-1/+1
* nir: Embed the shader_info in the nir_shader againJason Ekstrand2017-05-091-9/+9
* i965/fs: Always provide a default LOD of 0 for TXS and TXLJason Ekstrand2017-04-041-9/+9
* nir: Rework conversion opcodesJason Ekstrand2017-03-141-24/+11
* i965/fs: Re-arrange conversion operationsJason Ekstrand2017-03-141-36/+31
* i965/fs: Use num_components from the SSA def in image intrinsicsJason Ekstrand2017-03-141-2/+1
* i965: Move the back-end compiler to src/intel/compilerJason Ekstrand2017-03-131-0/+4679
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